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Shinei-Nouzen-Arch/FPGA-Agent
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View on GitHubAdd to my skills
Verified commit b60a52ea4d7498cd7e63ba72715c6eb3cf15ec66
git clone --filter=blob:none --no-checkout https://github.com/Shinei-Nouzen-Arch/FPGA-Agent.git .hotskills/shinei-nouzen-arch-fpga-agent && git -C .hotskills/shinei-nouzen-arch-fpga-agent checkout --detach b60a52ea4d7498cd7e63ba72715c6eb3cf15ec66
# Copy each selected skill directory from .hotskills/shinei-nouzen-arch-fpga-agent into .agents/skills/<skill-name>/181GitHub stars
1star in 7 days
10skills in this repository
0commits in 30 days
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Individual skills in this repository
- run-agentic-dse
DSE-agent - vitis-hls-synthesis
vitis-hls-synthesis - vivado-analysis
vivado-analysis - vivado-constraints
vivado-constraints - vivado-debug
vivado-debug - vivado-impl
vivado-impl - vivado-sim
vivado-sim - vivado-synth
vivado-synth - vivado-tcl
vivado-tcl - vivado-timing-closure
vivado-timing-closure
How it works
run-agentic-dse
When your agent uses it
Initialize, run, resume, and inspect FPGA HLS design-space exploration with Explorer, Exploiter, and Innovator workers. Also use for read-only requirement review, architecture advice, Pareto analysis, and convergence diagnosis without automatically launching experiments.
What it loads into context
Frontmatter
59 tokensAlways available to the agent
SKILL.md
2,065 tokensWhen the skill is activated
Reference documents
8,114 tokensLoaded on request
Token counts are estimates. Scripts run separately; they are not counted as reference context.
The playbook
- Roots and routing
- Publication boundary
- Initialize or reconcile an authorized run
- Execute rounds
- Stopping and completion
- Status and recovery
Scripts executed separately
src/artifacts.pysrc/hls_driver.pysrc/hls_run.shsrc/hypervolume.pytests/test_hls_artifacts.pytests/test_hypervolume.pytests/test_package.py
Files
AGENTS.mddoc4,841 bytesSKILL.mdcore10,606 bytesagent.mddoc324 bytesagents/openai.yamlasset225 bytesevals/scenarios.jsonasset4,643 bytesprompts/architect.mddoc3,185 bytesprompts/coding_style.mddoc3,631 bytesprompts/exploiter.mddoc1,603 bytesprompts/explorer.mddoc1,525 bytesprompts/hardware_checklist.mddoc3,502 bytesprompts/hls_tool_reference.mddoc3,662 bytesprompts/innovator.mddoc1,830 bytesprompts/req_parser.mddoc3,715 bytesreferences/contracts.mddoc8,083 bytesreferences/worker-workflow.mddoc5,407 bytessrc/artifacts.pyruns8,224 bytessrc/hls_driver.pyruns7,864 bytessrc/hls_run.shruns354 bytessrc/hypervolume.pyruns11,186 bytessrc/req_parser_schema.jsonasset2,317 bytestests/test_hls_artifacts.pyruns11,109 bytestests/test_hypervolume.pyruns9,095 bytestests/test_package.pyruns2,272 bytes
No excerpt is shown for this license. Read the source on GitHub.
View the complete source on GitHubvitis-hls-synthesis
When your agent uses it
Vitis HLS synthesis assistant for C/C++ to RTL conversion. Covers kernel development, pragma optimization, interface configuration, and synthesis report analysis. For post-synthesis implementation use vivado-impl, for timing analysis use vivado-analysis, for hardware debug use vivado-debug.
What it loads into context
Frontmatter
67 tokensAlways available to the agent
SKILL.md
1,726 tokensWhen the skill is activated
Reference documents
17,718 tokensLoaded on request
Token counts are estimates. Scripts run separately; they are not counted as reference context.
The playbook
- When to Use This Skill
- Workflow
- Quick Reference
- Common Scenario Examples
- Related Skills
Scripts executed separately
examples/Design_Tutorials/02-Beamformer/Makefileexamples/Design_Tutorials/02-Beamformer/project.pyexamples/Feature_Tutorials/02-Beamformer_Analysis/Makefileexamples/Feature_Tutorials/02-Beamformer_Analysis/project.pyexamples/Introductory_Examples/Array/array_partition_block_cyclic/run.pyexamples/Introductory_Examples/Array/array_partition_block_cyclic/run_vitis_commandline.shexamples/Introductory_Examples/Array/array_partition_complete/run.pyexamples/Introductory_Examples/Array/array_partition_complete/run_vitis_commandline.shexamples/Introductory_Examples/DSP/DSP_Intrinsic_Library/systolic_fir/run.pyexamples/Introductory_Examples/DSP/DSP_Intrinsic_Library/systolic_fir/run_vitis_commandline.shexamples/Introductory_Examples/DSP/DSP_Intrinsic_Library/systolic_fir_using_complex/run.pyexamples/Introductory_Examples/DSP/DSP_Intrinsic_Library/systolic_fir_using_complex/run_vitis_commandline.shexamples/Introductory_Examples/DSP/DSP_Intrinsic_Library/transposed_fir/run.pyexamples/Introductory_Examples/DSP/DSP_Intrinsic_Library/transposed_fir/run_vitis_commandline.shexamples/Introductory_Examples/DSP/fft/interface_array/run.pyexamples/Introductory_Examples/DSP/fft/interface_array_float_ssr2/run.pyexamples/Introductory_Examples/DSP/fft/interface_stream/run.pyexamples/Introductory_Examples/DSP/fft/interface_stream_float_ssr2/run.pyexamples/Introductory_Examples/DSP/fft/logicore_fft_float_ssr/generate_fft_data.pyexamples/Introductory_Examples/DSP/fft/logicore_fft_float_ssr/plot_fft_data.pyexamples/Introductory_Examples/DSP/fft/logicore_fft_float_ssr/run.pyexamples/Introductory_Examples/DSP/fir/decimator/run.pyexamples/Introductory_Examples/Interface/Memory/burst_rw/run_vitis_commandline.shexamples/Introductory_Examples/Interface/Memory/lmem_2rw/run_vitis_commandline.shexamples/Introductory_Examples/Migration/python_scripts/run.pyexamples/Introductory_Examples/Migration/python_scripts/run_with_external_config.pyexamples/Introductory_Examples/Migration/vitis_unified_cli/Makefileexamples/Introductory_Examples/Misc/rtl_as_blackbox/run.pyexamples/Introductory_Examples/Modeling/conditional_control_of_pragmas/using_defines/run.pyexamples/Introductory_Examples/Modeling/conditional_control_of_pragmas/using_template_function/run.pyexamples/Introductory_Examples/Modeling/using_C++_templates/run.pyexamples/Introductory_Examples/Modeling/using_C++_templates_for_multiple_instances/run.pyexamples/Introductory_Examples/Modeling/using_ap_float_accumulator/run.pyexamples/Introductory_Examples/Modeling/using_ap_float_accumulator/run_vitis_commandline.shexamples/Introductory_Examples/Modeling/using_array_stencil_1d/run.pyexamples/Introductory_Examples/Modeling/using_array_stencil_2d/run.pyexamples/Introductory_Examples/Pipelining/Loops/using_free_running_pipeline/run.pyexamples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/autorestart/run.pyexamples/Introductory_Examples/Task_level_Parallelism/Control_driven/directio/ap_hs/run.pyexamples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_axilite_with_directio/run.pyexamples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_directio_hs_in_tasks/run.pyexamples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_directio_none_in_tasks/run.pyexamples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_maxi_in_tasks/run.py
Files
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No excerpt is shown for this license. Read the source on GitHub.
View the complete source on GitHubvivado-analysis
When your agent uses it
Use this skill when the user needs Vivado design analysis, timing report interpretation, or timing-closure diagnosis. Covers report_timing/report_timing_summary, slack and path analysis, clock skew/uncertainty, report_qor_assessment/suggestions, report_design_analysis for congestion and complexity, report_methodology, utilization, CDC/DRC/bus skew reports, message severity, waivers, and setup/hold closure strategy. This skill interprets reports and recommends next analysis steps. For TCL execution use vivado-tcl, for constraint changes use vivado-constraints, for implementation directives use vivado-impl, for full timing closure workflows use vivado-timing-closure.
What it loads into context
Frontmatter
146 tokensAlways available to the agent
SKILL.md
3,081 tokensWhen the skill is activated
Reference documents
4,548 tokensLoaded on request
Token counts are estimates. Scripts run separately; they are not counted as reference context.
The playbook
- Timing Path Fundamentals
- Max/Min Delay Analysis Corner Selection
- Report Selection Guide
- Timing Report Header Fields
- Clock Phase Shift Mode (Device Defaults)
- QoR Assessment Interpretation (report_qor_assessment)
- QoR Suggestions Workflow
- Design Analysis Interpretation (report_design_analysis)
- Timing Closure Decision Tree
- Message Severity Levels
- Design Check Waiver System
- Synthesis Analysis & Closure Techniques
- Configurable Report Strategies
Files
REFERENCE.mddoc19,227 bytesSKILL.mdcore13,443 bytesSKILL.mdcore13,443 bytesagents/openai.yamlasset196 bytes
No excerpt is shown for this license. Read the source on GitHub.
View the complete source on GitHubvivado-constraints
When your agent uses it
Use this skill when the user needs help writing XDC/SDC timing or physical constraints for Vivado FPGA designs. This includes clock definitions (create_clock, create_generated_clock, virtual clocks), I/O delay constraints (set_input_delay, set_output_delay, DDR timing), timing exceptions (set_false_path, set_multicycle_path, set_max_delay, set_min_delay), clock domain crossing (CDC) constraints (set_clock_groups, set_bus_skew), clock uncertainty/jitter/latency, physical constraints (IOSTANDARD, PACKAGE_PIN, LOC, Pblock, placement, routing), XDC precedence rules, constraint scoping (SCOPED_TO_REF), constraint ordering optimization, or constraint debugging (check_timing, report_exceptions, report_clock_interaction). Trigger when the user mentions XDC, SDC, timing constraints, clock constraints, IO delay, false path, multicycle path, clock groups, or physical pin assignment. For timing report interpretation and analysis use vivado-analysis.
What it loads into context
Frontmatter
209 tokensAlways available to the agent
SKILL.md
3,903 tokensWhen the skill is activated
Reference documents
3,639 tokensLoaded on request
Token counts are estimates. Scripts run separately; they are not counted as reference context.
The playbook
- XDC File Management
- Clock Definition Guide
- Clock Latency, Jitter, Uncertainty
- I/O Delay Templates
- Timing Exceptions
- XDC Precedence Rules
- CDC Constraints
- Constraint Ordering for Performance
- Constraint Validation Commands
Files
REFERENCE.mddoc12,505 bytesSKILL.mdcore13,801 bytesSKILL.mdcore13,801 bytesSKILL.mdcore13,801 bytesSKILL.mdcore13,801 bytesSKILL.mdcore13,801 bytesSKILL.mdcore13,801 bytesSKILL.mdcore13,801 bytesSKILL.mdcore13,801 bytesagents/openai.yamlasset199 bytes
No excerpt is shown for this license. Read the source on GitHub.
View the complete source on GitHubvivado-debug
When your agent uses it
Use this skill when the user needs help with Vivado in-system debugging, hardware programming, or debug core configuration. This includes ILA (Integrated Logic Analyzer) configuration and trigger strategies, VIO (Virtual I/O) usage for signal monitoring and control, JTAG-to-AXI Master for AXI transaction generation, mark_debug attribute and debug probing flows (Netlist Insertion, HDL Instantiation), Set Up Debug Wizard, ILA cross-trigger architecture, debug core timing impact and mitigation, Vivado Hardware Manager operation, FPGA/SoC device programming, Versal debugging architecture (AXI4 Debug Hub, CIPS integration), SVF file programming, debug clock requirements, and common debug error troubleshooting. This skill provides debugging strategy and decision-making knowledge — for TCL command execution use vivado-tcl, for implementation strategies use vivado-impl, for timing analysis use vivado-analysis.
What it loads into context
Frontmatter
187 tokensAlways available to the agent
SKILL.md
4,707 tokensWhen the skill is activated
Reference documents
8,178 tokensLoaded on request
Token counts are estimates. Scripts run separately; they are not counted as reference context.
The playbook
- Debug Core Selection
- Debug Probing Flow Selection
- mark_debug Attribute
- ILA Configuration Decisions
- ILA Cross-Trigger
- VIO Usage Guide
- JTAG-to-AXI Master
- Versal Debug Architecture
- Debug Timing Impact & Mitigation
- Hardware Debug Six-Step Flow
- Debug Clock Requirements
- Common Error Troubleshooting and Reporting
Files
REFERENCE.mddoc24,934 bytesSKILL.mdcore19,284 bytesSKILL.mdcore19,284 bytesSKILL.mdcore19,284 bytesagents/openai.yamlasset186 bytesreferences/debug-troubleshooting.mddoc5,186 bytes
No excerpt is shown for this license. Read the source on GitHub.
View the complete source on GitHubvivado-impl
When your agent uses it
Use this skill when the user needs Vivado implementation strategy selection or optimization. Covers opt_design, power_opt_design, place_design, phys_opt_design, route_design, implementation directives/options, congestion-driven placement, fanout/placement/routing/SLR/register physical optimization, hold fixing, incremental implementation, ECO flow, and implementation run strategies for performance, congestion, area, and power. This skill chooses implementation-phase tactics and tradeoffs. For TCL command generation/execution use vivado-tcl, for synthesis use vivado-synth, for constraints use vivado-constraints, for report interpretation use vivado-analysis, for end-to-end timing closure use vivado-timing-closure.
What it loads into context
Frontmatter
146 tokensAlways available to the agent
SKILL.md
3,723 tokensWhen the skill is activated
Reference documents
3,762 tokensLoaded on request
Token counts are estimates. Scripts run separately; they are not counted as reference context.
The playbook
- Implementation Flow Overview
- opt_design — Logic Optimization
- place_design — Placement
- phys_opt_design — Physical Optimization
- route_design — Routing
- power_opt_design — Power Optimization
- Incremental Implementation
- Congestion Analysis & Resolution
- Predefined Implementation Strategies (Project Mode)
Files
REFERENCE.mddoc13,467 bytesSKILL.mdcore14,743 bytesagents/openai.yamlasset204 bytesexamples/ug906/TIMING-201/after/single_sdp_ram.svasset1,867 bytesexamples/ug906/TIMING-201/before/single_sdp_ram.svasset1,862 bytesexamples/ug906/TIMING-202/after/wide_mulitplier.svasset1,063 bytesexamples/ug906/TIMING-202/before/wide_mulitplier.svasset898 bytesexamples/ug906/UTIL-203/after/sp_rom.svasset28,620 bytesexamples/ug906/UTIL-203/before/sp_rom.vasset2,479 bytes
No excerpt is shown for this license. Read the source on GitHub.
View the complete source on GitHubvivado-sim
When your agent uses it
Use this skill when the user needs help with Vivado simulation strategy, flow selection, and debugging. This includes behavioral simulation (RTL functional verification), post-synthesis simulation (netlist functional verification), post-implementation timing simulation (SDF back-annotation, timing verification), Vivado Simulator xsim usage (xvlog/xvhdl/xelab/xsim three-step flow, launch_simulation Project Mode), third-party simulator integration (Questa/ModelSim/VCS/Xcelium/Riviera/ActiveHDL, compile_simlib, export_simulation), SAIF/VCD power simulation (open_saif/log_saif, open_vcd/log_vcd, read_saif + report_power), simulation netlist generation (write_verilog -mode funcsim/timesim, write_sdf), xsim debugging commands (add_force, add_wave, log_wave, add_bp, step, run, restart, get_objects, get_value), simulation properties and settings, glbl.v usage, or any question about choosing the right simulation approach for verification or power analysis.
What it loads into context
Frontmatter
224 tokensAlways available to the agent
SKILL.md
3,183 tokensWhen the skill is activated
Reference documents
3,723 tokensLoaded on request
Token counts are estimates. Scripts run separately; they are not counted as reference context.
The playbook
- Simulation Flow Overview
- Vivado Simulator (xsim) — Project Mode
- Vivado Simulator (xsim) — Non-Project Mode (Scripted)
- xsim Runtime / Debug Commands
- Timing Simulation (Post-Implementation)
- Third-Party Simulator Integration
- SAIF/VCD Power Simulation
- Simulation Properties Quick Reference
Scripts executed separately
evals/run_eval.sh
Files
REFERENCE.mddoc14,186 bytesSKILL.mdcore11,812 bytesSKILL.mdcore11,812 bytesSKILL.mdcore11,812 bytesSKILL.mdcore11,812 bytesagents/openai.yamlasset200 bytesevals/run_eval.shruns1,759 bytesevals/trigger_eval.jsonasset5,444 bytes
No excerpt is shown for this license. Read the source on GitHub.
View the complete source on GitHubvivado-synth
When your agent uses it
Use this skill when the user needs help with Vivado synthesis strategy selection, synthesis attribute configuration, synth_design option tuning, resource inference control (RAM/DSP/SRL/BRAM), hierarchy optimization (flatten_hierarchy, KEEP_HIERARCHY), OOC (out-of-context) synthesis, incremental synthesis, RTL linting, Block-Level synthesis (BLOCK_SYNTH), or any synthesis optimization decision. Trigger when the user mentions synthesis strategies, synthesis directives, synthesis attributes, resource mapping control, FSM encoding, retiming, or asks how to optimize synthesis results for area/timing/power. This skill provides decision-making knowledge — for TCL command execution, use vivado-tcl skill.
What it loads into context
Frontmatter
146 tokensAlways available to the agent
SKILL.md
3,742 tokensWhen the skill is activated
Reference documents
3,917 tokensLoaded on request
Token counts are estimates. Scripts run separately; they are not counted as reference context.
The playbook
- synth_design Complete Options
- Strategy Decision Table
- Synthesis Attributes Quick Reference (by scenario)
- Block-Level Synthesis (BLOCK_SYNTH)
- OOC (Out-of-Context) Synthesis
- Incremental Synthesis
- RTL Linter
- Synthesis-Stage Constraints
- Attribute Propagation Rules
Files
REFERENCE.mddoc13,656 bytesSKILL.mdcore14,335 bytesagents/openai.yamlasset192 bytesexamples/asym_ram_sdp_read_wider.vasset1,454 bytesexamples/asym_ram_sdp_write_wider.vasset1,465 bytesexamples/asym_ram_tdp_read_first.vasset1,642 bytesexamples/asym_ram_tdp_write_first.vasset1,650 bytesexamples/black_box_1.vasset325 bytesexamples/bytewrite_ram_1b.vasset864 bytesexamples/bytewrite_tdp_ram_nc.vasset2,153 bytesexamples/bytewrite_tdp_ram_readfirst2.vasset2,081 bytesexamples/bytewrite_tdp_ram_rf.vasset1,704 bytesexamples/bytewrite_tdp_ram_wf.vasset2,322 bytesexamples/cmacc.vasset2,959 bytesexamples/cmult.vasset1,612 bytesexamples/convergentRoundingEven.vasset1,552 bytesexamples/convergentRoundingOdd.vasset1,510 bytesexamples/dynamic_shift_registers_1.vasset413 bytesexamples/dynpreaddmultadd.vasset973 bytesexamples/finish_ignored_1.vasset421 bytesexamples/finish_supported_1.vasset653 bytesexamples/fsm_1.vasset872 bytesexamples/functions_1.vasset697 bytesexamples/functions_constant.vasset621 bytesexamples/latches.vasset297 bytesexamples/macc.vasset1,129 bytesexamples/mult_unsigned.vasset553 bytesexamples/parameter_1.vasset617 bytesexamples/parameter_generate_for_1.vasset529 bytesexamples/presubmult.vasset953 bytesexamples/procedure_package_1.vasset1,432 bytesexamples/rams_20c.dataasset576 bytesexamples/rams_dist.vasset382 bytesexamples/rams_init_file.dataasset2,112 bytesexamples/rams_init_file.vasset415 bytesexamples/rams_pipeline.vasset700 bytesexamples/rams_sdp_3d.svasset1,213 bytesexamples/rams_sdp_struct.svasset871 bytesexamples/rams_sp_3d.svasset948 bytesexamples/rams_sp_nc.vasset382 bytesexamples/rams_sp_rf.vasset375 bytesexamples/rams_sp_rf_rst.vasset504 bytesexamples/rams_sp_rom.vasset1,748 bytesexamples/rams_sp_rom_1.vasset2,427 bytesexamples/rams_sp_struct.svasset787 bytesexamples/rams_sp_wf.vasset445 bytesexamples/rams_tdp_3d.svasset1,496 bytesexamples/rams_tdp_rf_rf.vasset573 bytesexamples/rams_tdp_struct.svasset1,109 bytesexamples/registers_1.vasset380 bytesexamples/sfir_even_symmetric_systolic_top.vasset2,638 bytesexamples/sfir_shifter.vasset475 bytesexamples/shift_registers_0.vasset398 bytesexamples/shift_registers_1.vasset466 bytesexamples/simple_dual_one_clock.vasset451 bytesexamples/simple_dual_two_clocks.vasset496 bytesexamples/squarediffmacc.vasset1,554 bytesexamples/squarediffmult.vasset944 bytesexamples/tasks_1.vasset568 bytesexamples/top.vasset326 bytesexamples/tristates_1.vasset226 bytesexamples/tristates_2.vasset170 bytesexamples/v_rams_20c.dataasset384 bytesexamples/xilinx_ultraram_single_port_no_change.vasset2,229 bytesexamples/xilinx_ultraram_single_port_read_first.vasset2,175 bytesexamples/xilinx_ultraram_single_port_write_first.vasset2,247 bytesexamples/xor_top.vasset1,272 bytes
No excerpt is shown for this license. Read the source on GitHub.
View the complete source on GitHubvivado-tcl
When your agent uses it
Generate, review, explain, and execute Vivado/Vitis TCL scripts for FPGA design flows, and verify their execution results. Covers project and non-project flows, synthesis, implementation, simulation, constraints, IP integration, and hardware programming. Use for explicit TCL requests or when scripting is needed to complete an already-authorized FPGA task; the user need not name TCL again. For pure report interpretation, strategy selection, constraint theory, or debug planning, use the relevant analysis, synthesis, implementation, constraints, or debug skill as the primary guide. Combine those skills with this one when execution and verification are needed.
What it loads into context
Frontmatter
130 tokensAlways available to the agent
SKILL.md
2,468 tokensWhen the skill is activated
Reference documents
6,574 tokensLoaded on request
Token counts are estimates. Scripts run separately; they are not counted as reference context.
The playbook
- Overview
- Critical Rules
- Execution Model
- Quick Reference: Project Mode Flow
- Quick Reference: Non-Project Mode Flow
- IP Integrator (Block Design)
- Hardware Programming
- Debug Core Insertion (ILA)
- TCL Syntax Tips
- Workflow Guidelines
- Common Part Numbers (examples)
Files
REFERENCE.mddoc24,829 bytesSKILL.mdcore10,056 bytesSKILL.mdcore10,056 bytesSKILL.mdcore10,056 bytesagents/openai.yamlasset202 bytes
No excerpt is shown for this license. Read the source on GitHub.
View the complete source on GitHubvivado-timing-closure
When your agent uses it
Vivado FPGA timing closure and optimization assistant. Covers systematic timing analysis, constraint validation, implementation strategy selection (place_design/phys_opt_design/route_design directives), pblock-based area constraints, RapidWright-assisted netlist optimization, and iterative convergence workflows. Use when users mention timing closure, WNS/TNS violations, Fmax improvement, FPGA timing optimization, DCP optimization, or post-route ECO fixes. Also trigger for questions about check_timing, report_qor_assessment/suggestions, methodology DRC, clock interaction analysis, fanout optimization, LUT merging, or critical path analysis.
What it loads into context
Frontmatter
130 tokensAlways available to the agent
SKILL.md
5,399 tokensWhen the skill is activated
Reference documents
7,020 tokensLoaded on request
Token counts are estimates. Scripts run separately; they are not counted as reference context.
The playbook
- Quick Decision Flow
- Timing Acceptance Criteria
- Layer 1: Constraint Validation (ALWAYS START HERE)
- Layer 2: Tool-Managed Implementation Optimization (May Change the Netlist)
- Layer 3: Pblock Area Constraints
- Layer 4: Netlist-Level Optimization (Use with Caution)
- Congestion Analysis & Resolution
- Design Complexity Analysis (Pre-Implementation)
- Clock Skew Reduction
- Clock Interaction Report Deep-Dive
- Detailed Baseline Setting Process (from UG949)
- Diagnosing Violation Root Causes
- Advanced Optimization Topics
- Key Principles
- References
Files
SKILL.mdcore25,221 bytesSKILL.mdcore25,221 bytesSKILL.mdcore25,221 bytesSKILL.mdcore25,221 bytesSKILL.mdcore25,221 bytesSKILL.mdcore25,221 bytesSKILL.mdcore25,221 bytesSKILL.mdcore25,221 bytesagents/openai.yamlasset206 bytesevals/evals.jsonasset2,769 bytesreferences/advanced-optimization.mddoc6,570 bytesreferences/diagnosis-guide.mddoc11,697 bytesreferences/methodology-checklist.mddoc12,461 bytes
No excerpt is shown for this license. Read the source on GitHub.
View the complete source on GitHubSkills included
- run-agentic-dse
- vitis-hls-synthesis
- vivado-analysis
- vivado-constraints
- vivado-debug
- vivado-impl
- vivado-sim
- vivado-synth
- vivado-tcl
- vivado-timing-closure
Repository facts
- License
- GPL-2.0
- Created
- Mar 27, 2026
- Last pushed
- Sep 5, 2026
- Forks
- 22
- Open issues
- 1
- Project activity
- Slowing
Before you install
Network or broad shellAutomated signals, not a guarantee
Checked Nov 6, 2026
Not fully analyzed: some files were too long, unreadable or missing. This never lowers the level.
Show 23 notes
vitis-hls-synthesis/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-analysis/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-constraints/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-constraints/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-constraints/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-constraints/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-constraints/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-constraints/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-constraints/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-debug/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-debug/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-sim/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-sim/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-sim/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-tcl/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-tcl/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-timing-closure/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-timing-closure/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-timing-closure/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzedvivado-timing-closure/SKILL.md:1Analysis incomplete: Referenced executable target unavailable; not analyzed
- No broad tool permissions
- 5 dangerous shell commandsin 4 files: vitis-hls-synthesis/REFERENCE.md:52 vitis-hls-synthesis/examples/Design_Tutorials/02-Beamformer/Makefile:18 vitis-hls-synthesis/examples/Feature_Tutorials/02-Beamformer_Analysis/Makefile:18 and 1 more
- 1,161 network referencesin 384 files: vitis-hls-synthesis/examples/Design_Tutorials/02-Beamformer/README.md:3 vitis-hls-synthesis/examples/Feature_Tutorials/02-Beamformer_Analysis/README.md:3 vitis-hls-synthesis/examples/Introductory_Examples/Array/array_partition_block_cyclic/matmul_partition.cpp:7 and 381 more
- No hidden or obfuscated text
- No instruction overrides
- 51 executable scriptsin 51 files: DSE-agent/src/artifacts.py:1 DSE-agent/src/hls_driver.py:1 DSE-agent/src/hls_run.sh:1 and 48 more
- No requests to vote in Hot
Show all 1,221 signals by file
DSE-agent/src/artifacts.py
- Executable scriptline 1
#!/usr/bin/env python3
DSE-agent/src/hls_driver.py
DSE-agent/src/hls_run.sh
- Executable scriptline 1
#!/usr/bin/env bash
DSE-agent/src/hypervolume.py
- Executable scriptline 1
#!/usr/bin/env python3
DSE-agent/tests/test_hls_artifacts.py
DSE-agent/tests/test_hypervolume.py
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DSE-agent/tests/test_package.py
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vitis-hls-synthesis/REFERENCE.md
vitis-hls-synthesis/examples/Design_Tutorials/02-Beamformer/Makefile
vitis-hls-synthesis/examples/Design_Tutorials/02-Beamformer/README.md
- Network accessline 3
<td align="center"> <picture> <source media="(prefers-color-scheme: dark)" srcset="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/logo-white-text.png"> - Network accessline 4
<picture> <source media="(prefers-color-scheme: dark)" srcset="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/logo-white-text.png"> <img alt="AMD logo" src="https://raw.githubusercontent.com/Xilinx/Image-Coll - Network accessline 5
<source media="(prefers-color-scheme: dark)" srcset="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/logo-white-text.png"> - Network accessline 6
<img alt="AMD logo" src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"> - Network accessline 7
</picture> <h1>AMD Vitis™ HLS Tutorials</h1> <a href="https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vitis.html">See Vitis™ Development Environment on amd.com</a> - Network accessline 8
<h1>AMD Vitis™ HLS Tutorials</h1> <a href="https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vitis.html">See Vitis™ Development Environment on amd.com</a> </td> - Network accessline 9
<a href="https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vitis.html">See Vitis™ Development Environment on amd.com</a> - Network accessline 216
<p class="sphinxhide" align="center"><sup><a href="https://www.amd.com/en/corporate/copyright">Terms and Conditions</a></sup></p>
vitis-hls-synthesis/examples/Design_Tutorials/02-Beamformer/project.py
- Executable scriptline 1
#!/usr/bin/env python3
vitis-hls-synthesis/examples/Feature_Tutorials/02-Beamformer_Analysis/Makefile
vitis-hls-synthesis/examples/Feature_Tutorials/02-Beamformer_Analysis/README.md
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<td align="center"> <picture> <source media="(prefers-color-scheme: dark)" srcset="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/logo-white-text.png"> - Network accessline 4
<picture> <source media="(prefers-color-scheme: dark)" srcset="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/logo-white-text.png"> <img alt="AMD logo" src="https://raw.githubusercontent.com/Xilinx/Image-Coll - Network accessline 5
<source media="(prefers-color-scheme: dark)" srcset="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/logo-white-text.png"> - Network accessline 6
<img alt="AMD logo" src="https://raw.githubusercontent.com/Xilinx/Image-Collateral/main/xilinx-logo.png" width="30%"> - Network accessline 7
</picture> <h1>AMD Vitis™ HLS Tutorials</h1> <a href="https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vitis.html">See Vitis™ Development Environment on amd.com</a> - Network accessline 8
<h1>AMD Vitis™ HLS Tutorials</h1> <a href="https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vitis.html">See Vitis™ Development Environment on amd.com</a> </td> - Network accessline 9
<a href="https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vitis.html">See Vitis™ Development Environment on amd.com</a> - Network accessline 255
<p class="sphinxhide" align="center"><sup><a href="https://www.amd.com/en/corporate/copyright">Terms and Conditions</a></sup></p>
vitis-hls-synthesis/examples/Feature_Tutorials/02-Beamformer_Analysis/project.py
- Executable scriptline 1
#!/usr/bin/env python3
vitis-hls-synthesis/examples/Introductory_Examples/Array/array_partition_block_cyclic/matmul_partition.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Array/array_partition_block_cyclic/matmul_partition.h
vitis-hls-synthesis/examples/Introductory_Examples/Array/array_partition_block_cyclic/matmul_partition_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Array/array_partition_block_cyclic/run.py
- Executable scriptline 1
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vitis-hls-synthesis/examples/Introductory_Examples/Array/array_partition_block_cyclic/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Array/array_partition_block_cyclic/run_vitis_commandline.sh
- Executable scriptline 1
#!/bin/sh
vitis-hls-synthesis/examples/Introductory_Examples/Array/array_partition_complete/matmul_partition.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Array/array_partition_complete/matmul_partition.h
vitis-hls-synthesis/examples/Introductory_Examples/Array/array_partition_complete/matmul_partition_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Array/array_partition_complete/run.py
- Executable scriptline 1
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vitis-hls-synthesis/examples/Introductory_Examples/Array/array_partition_complete/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Array/array_partition_complete/run_vitis_commandline.sh
- Executable scriptline 1
#!/bin/sh
vitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/systolic_fir/run.py
- Executable scriptline 1
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vitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/systolic_fir/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/systolic_fir/run_vitis_commandline.sh
- Executable scriptline 1
#!/bin/sh
vitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/systolic_fir/systolic_fir.cpp
vitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/systolic_fir/systolic_fir.h
vitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/systolic_fir/systolic_fir_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/systolic_fir_using_complex/run.py
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vitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/systolic_fir_using_complex/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/systolic_fir_using_complex/run_vitis_commandline.sh
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vitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/transposed_fir/run.py
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vitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/transposed_fir/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/transposed_fir/run_vitis_commandline.sh
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#!/bin/sh
vitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/transposed_fir/transposed_fir.cpp
vitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/transposed_fir/transposed_fir.h
vitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/transposed_fir/transposed_fir_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_array/fft_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_array/fft_top.cpp
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_array/fft_top.h
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_array/run.py
- Executable scriptline 1
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vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_array/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_array_float_ssr2/fft_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_array_float_ssr2/fft_top.cpp
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_array_float_ssr2/fft_top.h
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_array_float_ssr2/run.py
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vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_array_float_ssr2/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_stream/fft_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_stream/fft_top.cpp
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_stream/fft_top.h
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_stream/run.py
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vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_stream/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_stream_float_ssr2/fft_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_stream_float_ssr2/fft_top.cpp
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_stream_float_ssr2/fft_top.h
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_stream_float_ssr2/run.py
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vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_stream_float_ssr2/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/logicore_fft_float_ssr/fft_top.cpp
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/logicore_fft_float_ssr/fft_top.h
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/logicore_fft_float_ssr/generate_fft_data.py
- Executable scriptline 1
#!/usr/bin/env python3
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/logicore_fft_float_ssr/new_fft_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/logicore_fft_float_ssr/plot_fft_data.py
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#!/usr/bin/env python3
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/logicore_fft_float_ssr/run.py
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vitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/logicore_fft_float_ssr/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fir/decimator/fir_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fir/decimator/fir_top.cpp
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fir/decimator/fir_top.h
vitis-hls-synthesis/examples/Introductory_Examples/DSP/fir/decimator/run.py
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vitis-hls-synthesis/examples/Introductory_Examples/DSP/fir/decimator/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/aggregation_of_m_axi_ports/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/aggregation_of_m_axi_ports/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/aggregation_of_m_axi_ports/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/aggregation_of_m_axi_ports/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/aggregation_of_nested_structs/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/aggregation_of_nested_structs/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/aggregation_of_nested_structs/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/aggregation_of_nested_structs/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/aggregation_of_struct/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/aggregation_of_struct/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/aggregation_of_struct/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/aggregation_of_struct/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/auto_disaggregation_of_struct/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/auto_disaggregation_of_struct/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/auto_disaggregation_of_struct/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/auto_disaggregation_of_struct/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/disaggregation_of_axis_port/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/disaggregation_of_axis_port/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/disaggregation_of_axis_port/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/disaggregation_of_axis_port/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/struct_ii_issue/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/struct_ii_issue/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/struct_ii_issue/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Aggregation_Disaggregation/struct_ii_issue/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/aliasing_axi_master_ports/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/aliasing_axi_master_ports/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/aliasing_axi_master_ports/test.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/aliasing_axi_master_ports/test_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/burst_rw/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/burst_rw/run_vitis_commandline.sh
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vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/burst_rw/vadd.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/burst_rw/vadd_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/cache/maxi_cache_conditional/dut.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/cache/maxi_cache_conditional/dut_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/cache/maxi_cache_conditional/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/cache/maxi_cache_locality/dut.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/cache/maxi_cache_locality/dut_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/cache/maxi_cache_locality/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/coefficient_filter/hamming_window.c
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/coefficient_filter/hamming_window.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/coefficient_filter/hamming_window_test.c
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/coefficient_filter/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/ecc_flags/ecc_flags.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/ecc_flags/ecc_flags.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/ecc_flags/ecc_flags_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/ecc_flags/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/lmem_2rw/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/lmem_2rw/run_vitis_commandline.sh
- Executable scriptline 1
#!/bin/sh
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/lmem_2rw/vadd.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/lmem_2rw/vadd_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/manual_burst/manual_burst_example/auto_burst_inference_failure/directives.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/manual_burst/manual_burst_example/auto_burst_inference_failure/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/manual_burst/manual_burst_example/auto_burst_inference_failure/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/manual_burst/manual_burst_example/auto_burst_inference_failure/example_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/manual_burst/manual_burst_example/auto_burst_inference_failure/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/manual_burst/manual_burst_example/manual_burst_inference_success/directives.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/manual_burst/manual_burst_example/manual_burst_inference_success/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/manual_burst/manual_burst_example/manual_burst_inference_success/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/manual_burst/manual_burst_example/manual_burst_inference_success/example_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/manual_burst/manual_burst_example/manual_burst_inference_success/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/manual_burst/manual_burst_with_conditionals/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/manual_burst/manual_burst_with_conditionals/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/manual_burst/manual_burst_with_conditionals/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/manual_burst/manual_burst_with_conditionals/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/max_widen_port_width/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/max_widen_port_width/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/max_widen_port_width/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/max_widen_port_width/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/memory_bottleneck/modified/mem_bottleneck_resolved.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/memory_bottleneck/modified/mem_bottleneck_resolved.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/memory_bottleneck/modified/mem_bottleneck_resolved_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/memory_bottleneck/modified/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/memory_bottleneck/original/mem_bottleneck.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/memory_bottleneck/original/mem_bottleneck.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/memory_bottleneck/original/mem_bottleneck_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/memory_bottleneck/original/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/ram_uram/resource_uram.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/ram_uram/resource_uram.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/ram_uram/resource_uram_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/ram_uram/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/rom_lookup_table_math/lookup_math.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/rom_lookup_table_math/lookup_math.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/rom_lookup_table_math/lookup_math_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/rom_lookup_table_math/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/using_axi_master/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/using_axi_master/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Memory/using_axi_master/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Register/using_axi_lite_with_user_defined_offset/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Register/using_axi_lite_with_user_defined_offset/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Register/using_axi_lite_with_user_defined_offset/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/axi_stream_to_master/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/axi_stream_to_master/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/axi_stream_to_master/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/axi_stream_to_master/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_array_of_streams/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_array_of_streams/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_array_of_streams/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_array_of_streams/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_axi_stream_with_custom_side_channel_data_2/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_axi_stream_with_custom_side_channel_data_2/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_axi_stream_with_custom_side_channel_data_2/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_axi_stream_with_custom_side_channel_data_2/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_axi_stream_with_side_channel_data/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_axi_stream_with_side_channel_data/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_axi_stream_with_side_channel_data/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_axi_stream_with_side_channel_data/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_axi_stream_with_struct/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_axi_stream_with_struct/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_axi_stream_with_struct/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_axis_array_stream_no_side_channel_data/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_axis_array_stream_no_side_channel_data/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Interface/Streaming/using_axis_array_stream_no_side_channel_data/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Migration/README.md
- Network accessline 17
# Online Documentation [Migrating-from-Vitis-HLS-to-the-Vitis-Unified-IDE](https://docs.amd.com/r/en-US/ug1399-vitis-hls/Migrating-from-Vitis-HLS-to-the-Vitis-Unified-IDE) - Network accessline 18
[Migrating-from-Vitis-HLS-to-the-Vitis-Unified-IDE](https://docs.amd.com/r/en-US/ug1399-vitis-hls/Migrating-from-Vitis-HLS-to-the-Vitis-Unified-IDE) - Network accessline 20
[Tcl-to-Config-File-Command-Map](https://docs.amd.com/r/en-US/ug1399-vitis-hls/Tcl-to-Config-File-Command-Map)
vitis-hls-synthesis/examples/Introductory_Examples/Migration/pointer_basic.c
vitis-hls-synthesis/examples/Introductory_Examples/Migration/pointer_basic.h
vitis-hls-synthesis/examples/Introductory_Examples/Migration/pointer_basic_test.c
vitis-hls-synthesis/examples/Introductory_Examples/Migration/python_scripts/run.py
vitis-hls-synthesis/examples/Introductory_Examples/Migration/python_scripts/run_with_external_config.py
- Executable scriptline 1
Executable file
vitis-hls-synthesis/examples/Introductory_Examples/Migration/tcl_scripts/pointer_basic.c
vitis-hls-synthesis/examples/Introductory_Examples/Migration/tcl_scripts/pointer_basic.h
vitis-hls-synthesis/examples/Introductory_Examples/Migration/tcl_scripts/pointer_basic_test.c
vitis-hls-synthesis/examples/Introductory_Examples/Migration/tcl_scripts/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Migration/tcl_scripts/run_vitis_unified.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Migration/vitis_unified_cli/Makefile
vitis-hls-synthesis/examples/Introductory_Examples/Misc/initialization_and_reset/static_array_RAM/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Misc/initialization_and_reset/static_array_RAM/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Misc/initialization_and_reset/static_array_RAM/test.h
vitis-hls-synthesis/examples/Introductory_Examples/Misc/initialization_and_reset/static_array_RAM/test_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Misc/initialization_and_reset/static_array_ROM/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Misc/initialization_and_reset/static_array_ROM/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Misc/initialization_and_reset/static_array_ROM/test.h
vitis-hls-synthesis/examples/Introductory_Examples/Misc/initialization_and_reset/static_array_ROM/test_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Misc/initialization_and_reset/static_array_of_struct_with_array_RAM/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Misc/initialization_and_reset/static_array_of_struct_with_array_RAM/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Misc/initialization_and_reset/static_array_of_struct_with_array_RAM/test.h
vitis-hls-synthesis/examples/Introductory_Examples/Misc/initialization_and_reset/static_array_of_struct_with_array_RAM/test_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Misc/initialization_and_reset/static_struct_with_array_RAM_Versal/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Misc/initialization_and_reset/static_struct_with_array_RAM_Versal/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Misc/initialization_and_reset/static_struct_with_array_RAM_Versal/test.h
vitis-hls-synthesis/examples/Introductory_Examples/Misc/initialization_and_reset/static_struct_with_array_RAM_Versal/test_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Misc/malloc_removed/malloc_removed.c
vitis-hls-synthesis/examples/Introductory_Examples/Misc/malloc_removed/malloc_removed.h
vitis-hls-synthesis/examples/Introductory_Examples/Misc/malloc_removed/malloc_removed_test.c
vitis-hls-synthesis/examples/Introductory_Examples/Misc/malloc_removed/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Misc/rtl_as_blackbox/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Misc/rtl_as_blackbox/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Misc/rtl_as_blackbox/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Misc/rtl_as_blackbox/rtl_model.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Misc/rtl_as_blackbox/rtl_model.v
vitis-hls-synthesis/examples/Introductory_Examples/Misc/rtl_as_blackbox/run.py
- Executable scriptline 1
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vitis-hls-synthesis/examples/Introductory_Examples/Misc/rtl_as_blackbox/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/basic_arithmetic/pointer_arith.c
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/basic_arithmetic/pointer_arith.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/basic_arithmetic/pointer_arith_test.c
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/basic_arithmetic/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/basic_pointers/pointer_basic.c
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/basic_pointers/pointer_basic.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/basic_pointers/pointer_basic_test.c
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/basic_pointers/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/multiple_pointers/pointer_multi.c
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/multiple_pointers/pointer_multi.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/multiple_pointers/pointer_multi_test.c
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/multiple_pointers/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/native_casts/pointer_cast_native.c
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/native_casts/pointer_cast_native.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/native_casts/pointer_cast_native_test.c
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/native_casts/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/stream_better/pointer_stream_better.c
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/stream_better/pointer_stream_better.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/stream_better/pointer_stream_better_test.c
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/stream_better/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/stream_good/pointer_stream_good.c
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/stream_good/pointer_stream_good.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/stream_good/pointer_stream_good_test.c
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/stream_good/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/using_double/pointer_double.c
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/using_double/pointer_double.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/using_double/pointer_double_test.c
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/Pointers/using_double/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/conditional_control_of_pragmas/using_defines/run.py
- Executable scriptline 1
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vitis-hls-synthesis/examples/Introductory_Examples/Modeling/conditional_control_of_pragmas/using_defines/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/conditional_control_of_pragmas/using_template_function/run.py
- Executable scriptline 1
Executable file
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/conditional_control_of_pragmas/using_template_function/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/fixed_point_sqrt/fxp_sqrt.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/fixed_point_sqrt/fxp_sqrt_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/fixed_point_sqrt/fxp_sqrt_top.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/fixed_point_sqrt/fxp_sqrt_top.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/fixed_point_sqrt/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/free_running_kernel_remerge_ii4to1/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/free_running_kernel_remerge_ii4to1/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/free_running_kernel_remerge_ii4to1/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/free_running_kernel_remerge_ii4to1/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_C++_templates/cpp_template.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_C++_templates/cpp_template.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_C++_templates/cpp_template_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_C++_templates/run.py
- Executable scriptline 1
Executable file
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_C++_templates/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_C++_templates_for_multiple_instances/cpp_template.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_C++_templates_for_multiple_instances/cpp_template.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_C++_templates_for_multiple_instances/cpp_template_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_C++_templates_for_multiple_instances/run.py
- Executable scriptline 1
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vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_C++_templates_for_multiple_instances/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_ap_float_accumulator/run.py
- Executable scriptline 1
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vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_ap_float_accumulator/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_ap_float_accumulator/run_vitis_commandline.sh
- Executable scriptline 1
#!/bin/sh
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_ap_float_accumulator/using_ap_float_accumulator.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_ap_float_accumulator/using_ap_float_accumulator.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_ap_float_accumulator/using_ap_float_accumulator_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_arbitrary_precision_arith/cpp_ap_int_arith.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_arbitrary_precision_arith/cpp_ap_int_arith.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_arbitrary_precision_arith/cpp_ap_int_arith_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_arbitrary_precision_arith/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_arbitrary_precision_casting/arbitrary_precision_casting.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_arbitrary_precision_casting/arbitrary_precision_casting.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_arbitrary_precision_casting/arbitrary_precision_casting_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_arbitrary_precision_casting/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_array_stencil_1d/dut.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_array_stencil_1d/hls_config.cfg
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_array_stencil_1d/run.py
- Executable scriptline 1
Executable file
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_array_stencil_1d/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_array_stencil_1d/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_array_stencil_2d/cmdlineparser.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_array_stencil_2d/cmdlineparser.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_array_stencil_2d/coefficients.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_array_stencil_2d/common.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_array_stencil_2d/filter2d_hw.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_array_stencil_2d/filter2d_sw.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_array_stencil_2d/run.py
- Executable scriptline 1
Executable file
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_array_stencil_2d/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_array_stencil_2d/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_fixed_point/cpp_ap_fixed.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_fixed_point/cpp_ap_fixed.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_fixed_point/cpp_ap_fixed_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_fixed_point/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_float_and_double/fp_mul_pow2.c
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_float_and_double/fp_mul_pow2.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_float_and_double/fp_mul_pow2_test.c
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_float_and_double/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_vectors/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_vectors/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_vectors/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/using_vectors/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/variable_bound_loops/loop_var.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/variable_bound_loops/loop_var.h
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/variable_bound_loops/loop_var_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Modeling/variable_bound_loops/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Functions/function_instantiate/example.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Functions/function_instantiate/example.h
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Functions/function_instantiate/example_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Functions/function_instantiate/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Functions/hier_func/hier_func4.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Functions/hier_func/hier_func4.h
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Functions/hier_func/hier_func4_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Functions/hier_func/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Loops/imperfect_loop/loop_imperfect.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Loops/imperfect_loop/loop_imperfect.h
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Loops/imperfect_loop/loop_imperfect_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Loops/imperfect_loop/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Loops/perfect_loop/loop_perfect.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Loops/perfect_loop/loop_perfect.h
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Loops/perfect_loop/loop_perfect_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Loops/perfect_loop/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Loops/pipelined_loop/loop_pipeline.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Loops/pipelined_loop/loop_pipeline.h
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Loops/pipelined_loop/loop_pipeline_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Loops/pipelined_loop/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Loops/using_free_running_pipeline/free_pipe_mult.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Loops/using_free_running_pipeline/free_pipe_mult.h
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Loops/using_free_running_pipeline/free_pipe_mult_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Loops/using_free_running_pipeline/run.py
- Executable scriptline 1
Executable file
vitis-hls-synthesis/examples/Introductory_Examples/Pipelining/Loops/using_free_running_pipeline/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/autorestart/diamond.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/autorestart/diamond.h
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/autorestart/diamond_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/autorestart/run.py
- Executable scriptline 1
Executable file
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/autorestart/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/merge_split/merge_load_balance/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/merge_split/merge_load_balance/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/merge_split/merge_load_balance/test.h
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/merge_split/merge_load_balance/test_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/merge_split/merge_round_robin/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/merge_split/merge_round_robin/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/merge_split/merge_round_robin/test.h
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/merge_split/merge_round_robin/test_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/merge_split/split_load_balance/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/merge_split/split_load_balance/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/merge_split/split_load_balance/test.h
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/merge_split/split_load_balance/test_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/merge_split/split_round_robin/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/merge_split/split_round_robin/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/merge_split/split_round_robin/test.h
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/merge_split/split_round_robin/test_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/simple_fifos/diamond.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/simple_fifos/diamond.h
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/simple_fifos/diamond_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/simple_fifos/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/using_fifos/diamond.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/using_fifos/diamond.h
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/using_fifos/diamond_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/using_fifos/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/using_stream_of_blocks/diamond.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/using_stream_of_blocks/diamond.h
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/using_stream_of_blocks/diamond_test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Channels/using_stream_of_blocks/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Patterns/input_bypass/dut.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Patterns/input_bypass/dut_sol.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Patterns/input_bypass/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Patterns/input_bypass/test_dut.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Patterns/middle_bypass/dut.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Patterns/middle_bypass/dut_sol.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Patterns/middle_bypass/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Patterns/middle_bypass/test_dut.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Patterns/output_bypass/dut.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Patterns/output_bypass/dut_sol.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Patterns/output_bypass/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Patterns/output_bypass/test_dut.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Patterns/using_stream_as_sync/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Patterns/using_stream_as_sync/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Patterns/using_stream_as_sync/test.h
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/Patterns/using_stream_as_sync/test_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/directio/ap_hs/dut.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/directio/ap_hs/dut.h
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/directio/ap_hs/run.py
- Executable scriptline 1
Executable file
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/directio/ap_hs/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Control_driven/directio/ap_hs/tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/handling_deadlock/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/handling_deadlock/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/handling_deadlock/test.h
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/handling_deadlock/test_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/mixed_control_and_data_driven/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/mixed_control_and_data_driven/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/mixed_control_and_data_driven/test.h
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/mixed_control_and_data_driven/test_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/simple_data_driven/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/simple_data_driven/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/simple_data_driven/test.h
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/simple_data_driven/test_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/unique_task_regions/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/unique_task_regions/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/unique_task_regions/test.h
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/unique_task_regions/test_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_axilite_with_directio/run.py
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_axilite_with_directio/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_axilite_with_directio/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_axilite_with_directio/test.h
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_axilite_with_directio/test_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_directio_hs_in_tasks/run.py
- Executable scriptline 1
Executable file
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_directio_hs_in_tasks/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_directio_hs_in_tasks/test.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_directio_hs_in_tasks/test.h
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_directio_hs_in_tasks/test_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_directio_none_in_tasks/adder_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_directio_none_in_tasks/adder_top.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_directio_none_in_tasks/adder_top.h
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_directio_none_in_tasks/run.py
- Executable scriptline 1
Executable file
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_directio_none_in_tasks/run_hls.tcl
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_maxi_in_tasks/dut.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_maxi_in_tasks/dut_tb.cpp
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_maxi_in_tasks/run.py
- Executable scriptline 1
Executable file
vitis-hls-synthesis/examples/Introductory_Examples/Task_level_Parallelism/Data_driven/using_maxi_in_tasks/run_hls.tcl
vivado-sim/evals/run_eval.sh
- Executable scriptline 1
#!/usr/bin/env bash
vivado-timing-closure/SKILL.md
- Network accessline 409
- AMD UG1292: UltraFast Design Methodology Timing Closure Quick Reference Guide - AMD XTP301: UltraFast Design Methodology Checklist - [AMD UG835: phys_opt_design](https://docs.amd.com/r/2025.2-English/ug835-vivado-tcl-commands/phys_opt_des - Network accessline 411
- [AMD UG835: phys_opt_design](https://docs.amd.com/r/2025.2-English/ug835-vivado-tcl-commands/phys_opt_design) — post-place/post-route operation and tool-managed netlist changes
How the signals fit together
Facts from a static read of the files at the pinned commit. They describe what the code does, not why.
Some files could not be read; the facts below still hold.
Signal confidence: 84 facts
- Executable script in code of a file that runsDSE-agent/src/artifacts.py:1High confidence
- Executable script in code of a file that runsDSE-agent/src/hls_driver.py:1High confidence
- Access to secrets in code of a file that runs: a variable, placeholder or call, not a stored valueDSE-agent/src/hls_driver.py:156Low confidence
- Executable script in code of a file that runsDSE-agent/src/hls_run.sh:1High confidence
- Executable script in code of a file that runsDSE-agent/src/hypervolume.py:1High confidence
- Executable script in prose of a testDSE-agent/tests/test_hls_artifacts.py:1Low confidence
- Access to secrets in code of a test: a variable, placeholder or call, not a stored valueDSE-agent/tests/test_hls_artifacts.py:214Low confidence
- Access to secrets in code of a test: a variable, placeholder or call, not a stored valueDSE-agent/tests/test_hls_artifacts.py:221Low confidence
- Executable script in prose of a testDSE-agent/tests/test_hypervolume.py:1Low confidence
- Executable script in prose of a testDSE-agent/tests/test_package.py:1Low confidence
- Dangerous shell operation in code of documentationvitis-hls-synthesis/REFERENCE.md:52Low confidence
- Dangerous shell operation in code of documentationvitis-hls-synthesis/REFERENCE.md:53Low confidence
- Executable script in code of a file that runsvitis-hls-synthesis/examples/Design_Tutorials/02-Beamformer/Makefile:1High confidence
- Dangerous shell operation in code of a file that runsvitis-hls-synthesis/examples/Design_Tutorials/02-Beamformer/Makefile:18High confidence
- Network access in prose of documentationvitis-hls-synthesis/examples/Design_Tutorials/02-Beamformer/README.md:3Low confidence
- Network access in prose of documentationvitis-hls-synthesis/examples/Design_Tutorials/02-Beamformer/README.md:4Low confidence
- Network access in prose of documentationvitis-hls-synthesis/examples/Design_Tutorials/02-Beamformer/README.md:5Low confidence
- Network access in prose of documentationvitis-hls-synthesis/examples/Design_Tutorials/02-Beamformer/README.md:6Low confidence
- Network access in prose of documentationvitis-hls-synthesis/examples/Design_Tutorials/02-Beamformer/README.md:7Low confidence
- Network access in prose of documentationvitis-hls-synthesis/examples/Design_Tutorials/02-Beamformer/README.md:8Low confidence
- Network access in prose of documentationvitis-hls-synthesis/examples/Design_Tutorials/02-Beamformer/README.md:9Low confidence
- Network access in code of documentationvitis-hls-synthesis/examples/Design_Tutorials/02-Beamformer/README.md:216Low confidence
- Executable script in code of a file that runsvitis-hls-synthesis/examples/Design_Tutorials/02-Beamformer/project.py:1High confidence
- Executable script in code of a file that runsvitis-hls-synthesis/examples/Feature_Tutorials/02-Beamformer_Analysis/Makefile:1High confidence
- Dangerous shell operation in code of a file that runsvitis-hls-synthesis/examples/Feature_Tutorials/02-Beamformer_Analysis/Makefile:18High confidence
- Network access in prose of documentationvitis-hls-synthesis/examples/Feature_Tutorials/02-Beamformer_Analysis/README.md:3Low confidence
- Network access in prose of documentationvitis-hls-synthesis/examples/Feature_Tutorials/02-Beamformer_Analysis/README.md:4Low confidence
- Network access in prose of documentationvitis-hls-synthesis/examples/Feature_Tutorials/02-Beamformer_Analysis/README.md:5Low confidence
- Network access in prose of documentationvitis-hls-synthesis/examples/Feature_Tutorials/02-Beamformer_Analysis/README.md:6Low confidence
- Network access in prose of documentationvitis-hls-synthesis/examples/Feature_Tutorials/02-Beamformer_Analysis/README.md:7Low confidence
- Network access in prose of documentationvitis-hls-synthesis/examples/Feature_Tutorials/02-Beamformer_Analysis/README.md:8Low confidence
- Network access in prose of documentationvitis-hls-synthesis/examples/Feature_Tutorials/02-Beamformer_Analysis/README.md:9Low confidence
- Network access in prose of documentationvitis-hls-synthesis/examples/Feature_Tutorials/02-Beamformer_Analysis/README.md:255Low confidence
- Executable script in code of a file that runsvitis-hls-synthesis/examples/Feature_Tutorials/02-Beamformer_Analysis/project.py:1High confidence
- Executable script in code of a file that runsvitis-hls-synthesis/examples/Introductory_Examples/Array/array_partition_block_cyclic/run.py:1High confidence
- Executable script in code of a file that runsvitis-hls-synthesis/examples/Introductory_Examples/Array/array_partition_block_cyclic/run_vitis_commandline.sh:1High confidence
- Executable script in code of a file that runsvitis-hls-synthesis/examples/Introductory_Examples/Array/array_partition_complete/run.py:1High confidence
- Executable script in code of a file that runsvitis-hls-synthesis/examples/Introductory_Examples/Array/array_partition_complete/run_vitis_commandline.sh:1High confidence
- Executable script in a comment of a file that runsvitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/systolic_fir/run.py:1Low confidence
- Executable script in code of a file that runsvitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/systolic_fir/run_vitis_commandline.sh:1High confidence
- Executable script in a comment of a file that runsvitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/systolic_fir_using_complex/run.py:1Low confidence
- Executable script in code of a file that runsvitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/systolic_fir_using_complex/run_vitis_commandline.sh:1High confidence
- Executable script in a comment of a file that runsvitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/transposed_fir/run.py:1Low confidence
- Executable script in code of a file that runsvitis-hls-synthesis/examples/Introductory_Examples/DSP/DSP_Intrinsic_Library/transposed_fir/run_vitis_commandline.sh:1High confidence
- Executable script in code of a file that runsvitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_array/run.py:1High confidence
- Executable script in code of a file that runsvitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_array_float_ssr2/run.py:1High confidence
- Executable script in code of a file that runsvitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_stream/run.py:1High confidence
- Executable script in code of a file that runsvitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/interface_stream_float_ssr2/run.py:1High confidence
- Executable script in code of a file that runsvitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/logicore_fft_float_ssr/generate_fft_data.py:1High confidence
- Executable script in code of a file that runsvitis-hls-synthesis/examples/Introductory_Examples/DSP/fft/logicore_fft_float_ssr/plot_fft_data.py:1High confidence
and 34 more
Works with
| Agent | Status | Evidence | Install to |
|---|---|---|---|
| Claude Code | Compatible | Standard SKILL.md DSE-agent/SKILL.md | .claude/skills/<skill-name>/ |
| Codex | Native | Manifest DSE-agent/AGENTS.md | .agents/skills/<skill-name>/ |
| Cursor | Compatible | Standard SKILL.md DSE-agent/SKILL.md | .cursor/skills/<skill-name>/ |
| Gemini CLI | Compatible | Standard SKILL.md DSE-agent/SKILL.md | .gemini/skills/<skill-name>/ |
| GitHub Copilot | Compatible | Standard SKILL.md DSE-agent/SKILL.md | .github/skills/<skill-name>/ |
| OpenCode | Compatible | Standard SKILL.md DSE-agent/SKILL.md | .opencode/skills/<skill-name>/ |
- Native The repository ships a manifest, folder or frontmatter field for this agent.
- Compatible A standard SKILL.md that this agent can read.
- Unknown No evidence either way.
Derived automatically from paths, manifests and frontmatter. Not tested on each agent.
