Individual skill

vivado-tcl

Generate, review, explain, and execute Vivado/Vitis TCL scripts for FPGA design flows, and verify their execution results. Covers project and non-project flows, synthesis, implementation, simulation, constraints, IP integration, and hardware programming. Use for explicit TCL requests or when scripting is needed to complete an already-authorized FPGA task; the user need not name TCL again. For pure report interpretation, strategy selection, constraint theory, or debug planning, use the relevant analysis, synthesis, implementation, constraints, or debug skill as the primary guide. Combine those skills with this one when execution and verification are needed.

vivado-tcl/SKILL.md

Source commit b60a52ea4d7498cd7e63ba72715c6eb3cf15ec66

What was checked

Matches the observed repository HEAD

Yes

Scanner rules are current

Yes

Repository scan complete

No

Skill scan complete

No

Observed behavior

Instructions only

Last checked

Nov 11, 2026

These are observations at the recorded commit, not a guarantee of safety. Review the source before running it.

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