Individual skill

vivado-timing-closure

Vivado FPGA timing closure and optimization assistant. Covers systematic timing analysis, constraint validation, implementation strategy selection (place_design/phys_opt_design/route_design directives), pblock-based area constraints, RapidWright-assisted netlist optimization, and iterative convergence workflows. Use when users mention timing closure, WNS/TNS violations, Fmax improvement, FPGA timing optimization, DCP optimization, or post-route ECO fixes. Also trigger for questions about check_timing, report_qor_assessment/suggestions, methodology DRC, clock interaction analysis, fanout optimization, LUT merging, or critical path analysis.

vivado-timing-closure/SKILL.md

Source commit b60a52ea4d7498cd7e63ba72715c6eb3cf15ec66

What was checked

Matches the observed repository HEAD

Yes

Scanner rules are current

Yes

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No

Skill scan complete

No

Observed behavior

Instructions only

Last checked

Nov 11, 2026

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