Individual skill
vivado-synth
Use this skill when the user needs help with Vivado synthesis strategy selection, synthesis attribute configuration, synth_design option tuning, resource inference control (RAM/DSP/SRL/BRAM), hierarchy optimization (flatten_hierarchy, KEEP_HIERARCHY), OOC (out-of-context) synthesis, incremental synthesis, RTL linting, Block-Level synthesis (BLOCK_SYNTH), or any synthesis optimization decision. Trigger when the user mentions synthesis strategies, synthesis directives, synthesis attributes, resource mapping control, FSM encoding, retiming, or asks how to optimize synthesis results for area/timing/power. This skill provides decision-making knowledge — for TCL command execution, use vivado-tcl skill.
vivado-synth/SKILL.md
Source commit b60a52ea4d7498cd7e63ba72715c6eb3cf15ec66
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- Matches the observed repository HEAD
- Yes
- Scanner rules are current
- Yes
- Repository scan complete
- No
- Skill scan complete
- Yes
- Observed behavior
- Instructions only
- Last checked
- Nov 11, 2026
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Repository context
- Repository stars (not skill ratings)
- 183
- Repository last updated
- Sep 5, 2026
- License
- GPL-2.0
Observed agent integration: No specific integration evidence. Standard SKILL.md installation does not imply verified compatibility.
- engineering Derived category
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REFERENCE.mddoc · 13,656 bytesSKILL.mdcore · 14,335 bytesagents/openai.yamlasset · 192 bytesexamples/asym_ram_sdp_read_wider.vasset · 1,454 bytesexamples/asym_ram_sdp_write_wider.vasset · 1,465 bytesexamples/asym_ram_tdp_read_first.vasset · 1,642 bytesexamples/asym_ram_tdp_write_first.vasset · 1,650 bytesexamples/black_box_1.vasset · 325 bytesexamples/bytewrite_ram_1b.vasset · 864 bytesexamples/bytewrite_tdp_ram_nc.vasset · 2,153 bytesexamples/bytewrite_tdp_ram_readfirst2.vasset · 2,081 bytesexamples/bytewrite_tdp_ram_rf.vasset · 1,704 bytesexamples/bytewrite_tdp_ram_wf.vasset · 2,322 bytesexamples/cmacc.vasset · 2,959 bytesexamples/cmult.vasset · 1,612 bytesexamples/convergentRoundingEven.vasset · 1,552 bytesexamples/convergentRoundingOdd.vasset · 1,510 bytesexamples/dynamic_shift_registers_1.vasset · 413 bytesexamples/dynpreaddmultadd.vasset · 973 bytesexamples/finish_ignored_1.vasset · 421 bytesexamples/finish_supported_1.vasset · 653 bytesexamples/fsm_1.vasset · 872 bytesexamples/functions_1.vasset · 697 bytesexamples/functions_constant.vasset · 621 bytesexamples/latches.vasset · 297 bytesexamples/macc.vasset · 1,129 bytesexamples/mult_unsigned.vasset · 553 bytesexamples/parameter_1.vasset · 617 bytesexamples/parameter_generate_for_1.vasset · 529 bytesexamples/presubmult.vasset · 953 bytesexamples/procedure_package_1.vasset · 1,432 bytesexamples/rams_20c.dataasset · 576 bytesexamples/rams_dist.vasset · 382 bytesexamples/rams_init_file.dataasset · 2,112 bytesexamples/rams_init_file.vasset · 415 bytesexamples/rams_pipeline.vasset · 700 bytesexamples/rams_sdp_3d.svasset · 1,213 bytesexamples/rams_sdp_struct.svasset · 871 bytesexamples/rams_sp_3d.svasset · 948 bytesexamples/rams_sp_nc.vasset · 382 bytesexamples/rams_sp_rf.vasset · 375 bytesexamples/rams_sp_rf_rst.vasset · 504 bytesexamples/rams_sp_rom.vasset · 1,748 bytesexamples/rams_sp_rom_1.vasset · 2,427 bytesexamples/rams_sp_struct.svasset · 787 bytesexamples/rams_sp_wf.vasset · 445 bytesexamples/rams_tdp_3d.svasset · 1,496 bytesexamples/rams_tdp_rf_rf.vasset · 573 bytesexamples/rams_tdp_struct.svasset · 1,109 bytesexamples/registers_1.vasset · 380 bytesexamples/sfir_even_symmetric_systolic_top.vasset · 2,638 bytesexamples/sfir_shifter.vasset · 475 bytesexamples/shift_registers_0.vasset · 398 bytesexamples/shift_registers_1.vasset · 466 bytesexamples/simple_dual_one_clock.vasset · 451 bytesexamples/simple_dual_two_clocks.vasset · 496 bytesexamples/squarediffmacc.vasset · 1,554 bytesexamples/squarediffmult.vasset · 944 bytesexamples/tasks_1.vasset · 568 bytesexamples/top.vasset · 326 bytesexamples/tristates_1.vasset · 226 bytesexamples/tristates_2.vasset · 170 bytesexamples/v_rams_20c.dataasset · 384 bytesexamples/xilinx_ultraram_single_port_no_change.vasset · 2,229 bytesexamples/xilinx_ultraram_single_port_read_first.vasset · 2,175 bytesexamples/xilinx_ultraram_single_port_write_first.vasset · 2,247 bytesexamples/xor_top.vasset · 1,272 bytes
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