Individual skill

memory-hierarchy-and-caches

Use when explaining cache levels, associativity, cache lines, false sharing, prefetching, or MESI coherence. Not for measuring and fixing cache misses in a program: use cpu-cache-opt.

.devin/skills/memory-hierarchy-and-caches/SKILL.md

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Repository last updated: Sep 28, 2026
License: Apache-2.0

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# Memory hierarchy and caches

## Contract

| Field | Bound contract |
|---|---|
| Trigger | Padding fixed a scaling problem and needs explaining, a struct layout for multicore needs choosing, a cache miss counter needs interpreting, or a DMA buffer disagrees with the CPU cache on an embedded SoC. |
| Authority | Read-only. The skill reads `getconf`, `lscpu`, and `perf stat` output and answers in chat. Nothing on disk changes, so there is nothing to roll back. No remote mutation. |
| Side effect | Chat output only. |
| Done | The answer names the level and the miss class involved, quotes the host's line size and cache sizes from the tools, and states the layout or access change with its condition. |

## Inputs

- Code or data layout (required): the struct, array, or access pattern in question.