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riscv-privileged

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Use when writing RISC-V M-mode or S-mode code: CSRs, trap handlers, PLIC and CLINT interrupts, OpenSBI payloads, Sv39 or Sv48 page tables, or QEMU virt boot. Not for user-mode asm: use assembly-riscv.

.devin/skills/riscv-privileged/SKILL.md

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Sep 28, 2026
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Apache-2.0

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# RISC-V privileged architecture

## Contract

| Field | Bound contract |
|---|---|
| Trigger | A kernel, hypervisor, or firmware for RISC-V needs privilege modes, CSR access, a trap entry, timer or external interrupts, OpenSBI integration, virtual memory, or a QEMU `virt` boot and GDB session. |
| Authority | Reversible local: writes only the kernel or firmware sources in the project directory the user names and the OpenSBI build output under its own `build/`; rollback is reverting the sources and deleting `build/`. No remote mutation. |
| Side effect | New or edited sources, an OpenSBI firmware image, and QEMU processes started for testing. |
| Done | The image boots on `qemu-system-riscv64 -machine virt`, an `ecall` from U-mode reaches the trap handler with `scause = 8`, the timer interrupt fires through SBI, a PLIC source is claimed and completed, and the kernel runs with `satp` pointing at a page table it built. |

## Inputs

- Which modes the target implements: M, S, and U (Linux-class), or M and U only (embedded).
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