Individual skill
verilog-basics-for-lowlevel
Use when reading RTL to understand hardware behavior, reset and clock domains, CDC synchronizers, APB/AHB/AXI bus protocols, or collaborating with hardware teams on SoC diagrams.
.devin/skills/verilog-basics-for-lowlevel/SKILL.md
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- Last checked
- Nov 4, 2026
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- Sep 28, 2026
- License
- Apache-2.0
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# Verilog basics for low-level engineers
## Contract
| Field | Bound contract |
|---|---|
| Trigger | A reference manual is unclear and the RTL settles the question, a clock-domain-crossing bug needs explaining, a bus transaction needs correlating with driver ordering, or an SoC block diagram needs reading with a hardware team. |
| Authority | Read-only. Emits analysis in chat; no file writes, no rollback needed. No remote mutation. |
| Side effect | An explanation of the RTL behavior in chat. Nothing is written. |
| Done | The hardware behavior behind the software question is stated in register-access terms, or the missing RTL or documentation is named. |
This skill gives reading literacy, not design skill. It does not replace an HDL course.
## Inputs