Individual skill
jetson-customize-pcie
Per-controller PCIe enable / disable / lanes / link-speed for a Jetson Thor or Orin custom carrier via ODMDATA + kernel-DT overlay. Do NOT use for UPHY lane allocation or endpoint-mode bring-up.
skills/jetson-customize-pcie/SKILL.md
Source commit fce3cca4170be75e82c64920654d56ee2811b005
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- Matches the observed repository HEAD
- Yes
- Scanner rules are current
- Yes
- Repository scan complete
- No
- Skill scan complete
- No
- Observed behavior
- Network or broad shell
- Last checked
- Nov 9, 2026
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Repository context
- Repository stars (not skill ratings)
- 3,917
- Repository last updated
- Nov 9, 2026
- License
- Apache-2.0
Observed agent integration: No specific integration evidence. Standard SKILL.md installation does not imply verified compatibility.
- agent-skills Repository topic
- agentic-ai Repository topic
- ai-agents Repository topic
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- cuda Repository topic
- developer-tools Repository topic
- llm Repository topic
- omniverse Repository topic
- bsp Declared skill tag
- phase-2 Declared skill tag
- io Declared skill tag
- pcie Declared skill tag
- engineering Derived category
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BENCHMARK.mddoc · 3,832 bytesSKILL.mdcore · 9,336 bytesSKILL.mdcore · 9,336 bytesevals/evals.jsonasset · 7,057 bytesreferences/gotchas.mddoc · 2,349 bytesreferences/procedure.mddoc · 15,200 bytesskill-card.mddoc · 3,760 bytesskill.oms.sigasset · 5,061 bytes
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# Customize PCIe (per-controller status / lanes / speed)
## Overview
PCIe on Tegra264 (Thor, `pcie@C0..C5`) and Tegra234 (Orin,
`pcie@C0..C10`) is split across multiple controllers that share the
UPHY lane pool with USB3 / MGBE / UFS. Each controller's runtime
behavior is determined by **two surfaces, both required**:
| Surface | Target | Authoritative for |
|---|---|---|
| ODMDATA `pcie@N_status=…` (+ `pcie@N_max-link-speed`, `pcie@N_pcie-mode`, `pcie@N_clk-scheme`, `pcie-cN-endpoint-enable`) | `/pcie/pcie@N` in BPMP DTB | UPHY lane power, refclk gating, controller-side power rails |
| Kernel-DT overlay on `&pcieN` | `/bus@0/pcie@<addr>` in kernel DTB | Kernel probe, lane width, link speed, RC/EP mode |
