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hsb-ip-create-top

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Create or explain fixed-format HSB FPGA_top.sv wrappers from validated HOLOLINK_def.svh files. Do not use for def generation or validation.

skills/hsb-ip-create-top/SKILL.md

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Nov 9, 2026
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Apache-2.0

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# HSB IP Create Top Skill

## Purpose

Create a fixed-format SystemVerilog top-level scaffold that instantiates `HOLOLINK_top` and declares the HSB-facing signals required by a validated `HOLOLINK_def.svh`.

This skill owns only the top-level scaffold around the HSB IP:

- SPDX/Apache license header
- `HOLOLINK_def.svh` include
- `FPGA_top` module shell
- HSB-facing signal declarations
- `HOLOLINK_top` instantiation
- comments/TODOs for top-level integration
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