Individual skill
fpga-hardware-design-and-review-guide
Comprehensive FPGA hardware design guide based on real-world project experience. Covers pipeline architecture, timing optimization, SystemVerilog coding patterns, CDC handling, and practical debugging techniques. Use this skill when: (1) designing FPGA modules with timing constraints, (2) implementing video processing or data path designs, (3) optimizing for resource utilization and timing closure, (4) reviewing RTL code for hardware implementation, (5) debugging synthesis or implementation issues.
SKILL.md
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- agent-skills Repository topic
- ai-assistant Repository topic
- claude-skill Repository topic
- fpga Repository topic
- rtl Repository topic
- skills Repository topic
- systemverilog Repository topic
- timing-optimization Repository topic
- veriloghdl Repository topic
- vivado Repository topic
- engineering Derived category
- design Derived category
- data Derived category
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LICENSEasset · 1,061 bytesPUBLISH_GUIDE.mddoc · 676 bytesREADME.mddoc · 4,664 bytesSKILL.mdcore · 8,156 bytesreferences/design-patterns.mddoc · 16,653 bytesreferences/device-selection.mddoc · 7,932 bytesreferences/troubleshooting.mddoc · 14,123 bytes
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# FPGA Hardware Design Guide
A practical FPGA hardware design guide based on real-world project experience.
## Core Design Philosophy
### 1. Pipeline Architecture First
When processing high-speed data streams (video, network packets), adopt multi-stage pipeline design:
- **Single-stage processing**: Combinational logic delay too large, prone to timing violations
- **Multi-stage pipeline**: Insert registers at each stage, distribute delay, increase clock frequency
- **Typical applications**: RGB-to-YUV conversion, image filtering, protocol parsing
**Real Case**: RGB-to-YUV converter with 5-stage pipeline