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asplos-experiments
Use when designing or auditing the evaluation of an ASPLOS paper — choosing among real silicon, FPGA prototypes, and simulators with cycle-accuracy caveats stated, selecting workload suites and baselines that hold up across three communities, attributing wins via ablation, and reporting energy, area, and overhead honestly.
ASPLOS-Skills/skills/asplos-experiments/SKILL.md
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# ASPLOS Experiments
An ASPLOS evaluation answers to three communities at once: architects who will audit
the modeling, OS people who will audit the workload realism, and PL people who will
audit what the software layer actually does. The section's core discipline is
**matching each claim to an instrument whose error model can carry it** — and saying
what that error model is.
## The instrument ladder
| Instrument | What it can prove | What it cannot | Must be reported |
|---|---|---|---|
| Real silicon | End-to-end effects, OS interactions, true tails | Designs needing hardware that doesn't exist | CPU/stepping, kernel + config, microcode, BIOS knobs (SMT/turbo/prefetchers), memory topology |
| FPGA prototype | Feasibility, cycle behavior of new logic at the prototype's clock | Absolute performance of an ASIC-class part | Board, clock, resource utilization, what was scaled down and why |