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review

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Review an FPGA project for hardware bugs - clock-domain crossings, pins, resets, address map, PYNQ overlay mistakes.

skills/review/SKILL.md

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Source commit e5b0d0adf6932b6135eaec0caf97614f2fb573da

What was checked

Matches the observed repository HEAD
Yes
Scanner rules are current
Yes
Repository scan complete
No
Skill scan complete
Yes
Observed behavior
Instructions only
Last checked
Nov 11, 2026

These are observations at the recorded commit, not a guarantee of safety. Review the source before running it.

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Repository context

Repository stars (not skill ratings)
27
Repository last updated
Nov 1, 2026
License
MIT

Observed agent integration: No specific integration evidence. Standard SKILL.md installation does not imply verified compatibility.

Files and excerpt

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Review the FPGA project in the folder given as arguments ($ARGUMENTS); if none, use the current folder.
Read `../fpga-project-analyzer/SKILL.md` (relative to this file's directory) and follow its workflow, including
`references/review.md`. Confirm each lint finding against the source, add what lint cannot see, and put every
confirmed finding (with file:line and fix) in the overlay. Reply with the diagram link (`?issues=1`) and the
findings ranked by severity.
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