Individual skill
explain
Explain an FPGA project (Vivado, Zynq, PYNQ) with an interactive drill-down diagram.
skills/explain/SKILL.md
Source commit e5b0d0adf6932b6135eaec0caf97614f2fb573da
What was checked
- Matches the observed repository HEAD
- Yes
- Scanner rules are current
- Yes
- Repository scan complete
- No
- Skill scan complete
- Yes
- Observed behavior
- Instructions only
- Last checked
- Nov 11, 2026
These are observations at the recorded commit, not a guarantee of safety. Review the source before running it.
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Repository context
- Repository stars (not skill ratings)
- 27
- Repository last updated
- Nov 1, 2026
- License
- MIT
Observed agent integration: No specific integration evidence. Standard SKILL.md installation does not imply verified compatibility.
- agent-skills Repository topic
- cdc Repository topic
- claude-code Repository topic
- fpga Repository topic
- pynq Repository topic
- rtl Repository topic
- verilog Repository topic
- vhdl Repository topic
- vivado Repository topic
- zynq Repository topic
- engineering Derived category
Files and excerpt
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Browse files
SKILL.mdcore · 583 bytes
Read excerpt
Explain the FPGA project in the folder given as arguments ($ARGUMENTS); if none, use the current folder.
Read `../fpga-project-analyzer/SKILL.md` (relative to this file's directory) and follow its workflow.
Focus on how the design works: a 3-8 word role note for every key block and 1-2 data-flow paths in the
overlay, then render the view. Reply with the diagram link and at most 6 short bullets.