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fpga-project-analyzer

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Analyze and explain existing AMD/Xilinx FPGA projects visually - Vivado block designs (.xpr, .bd, .hwh, .xsa, BD Tcl), Verilog/SystemVerilog/VHDL, PYNQ overlays and notebooks, HLS/bare-metal C, device trees, timing/DRC reports and build logs. Builds a drill-down Vivado-style diagram (block design -> IP -> RTL -> registers) and finds bugs - clock-domain crossings, unconstrained I/O, reset polarity, address map, interrupts, PYNQ overlay mistakes. Use when asked to understand, review, document or debug an FPGA, Zynq, MPSoC or PYNQ project, or a failed Vivado build.

skills/fpga-project-analyzer/SKILL.md

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Nov 1, 2026
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MIT

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# FPGA Project Analyzer

Scripts read the project; you read their compact output. Do not open .bd/.hwh/.xpr/report files directly.
`FPA` below stands for `python3 <this skill's directory>/scripts/fpa.py`; type the full command each time
(a shell variable does not word-split in zsh). Outputs go to `<project>/.fpa/`.

## Workflow
1. `FPA build <project>` - extracts everything, runs the checks, prints a ~40-line summary
   (blocks, clock domains, streams, AXI-MM, IRQ -> GIC/DT numbers, address map, software refs, reports, findings).
   Repo with several boards/builds or a Makefile flow: point it at the build's own lists instead of scanning,
   e.g. `--src sim/plps.d --src sim/psbd.d` (make .d / .f / .lst files, dirs or globs; repeatable).
2. Drill into what matters, never the whole tree:
   - `FPA show <project> <block>` one block (`/` = top, `/stream_proc/scaler_0` = nested): pins, peers,
     net names, clock domains, address, registers, software refs, src file:line; add `--nets` to list the
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