Individual skill
verilog-sv-language
Expert-level Verilog and SystemVerilog knowledge following IEEE 1800 standards. Generates synthesizable RTL code with proper coding styles and constructs.
library/specializations/fpga-programming/skills/verilog-sv-language/SKILL.md
Source commit feb68abe397acc14f32b34984975c48fedba2b33
What was checked
- Matches the observed repository HEAD
- Yes
- Scanner rules are current
- Yes
- Repository scan complete
- No
- Skill scan complete
- No
- Observed behavior
- Network or broad shell
- Last checked
- Nov 9, 2026
These are observations at the recorded commit, not a guarantee of safety. Review the source before running it.
Install this skill
Choose an agent in your Stack or copy a command below. Commands fetch the pinned commit and copy only this skill directory. Existing destinations are refused. Copying a command does not install anything.
An install command is unavailable: current rules, complete repository and skill scans, an eligible behavior level and a permitted license are required.
Repository context
- Repository stars (not skill ratings)
- 1,901
- Repository last updated
- Nov 1, 2026
- License
- MIT
Observed agent integration: No specific integration evidence. Standard SKILL.md installation does not imply verified compatibility.
- agent-orchestration Repository topic
- agent-skills Repository topic
- agentic-ai Repository topic
- agentic-workflow Repository topic
- ai-automation Repository topic
- babysitter Repository topic
- claude-code Repository topic
- claude-skills Repository topic
- trustworthy-ai Repository topic
- vibe-coding Repository topic
- engineering Derived category
Files and excerpt
File metadata and permitted, redacted excerpts come from the recorded scan. Source links are pinned to that commit.
Read excerpt
# Verilog/SystemVerilog Language Skill
Expert skill for Verilog and SystemVerilog development following IEEE 1364 and IEEE 1800 standards. Provides deep expertise in synthesizable RTL code generation, proper construct usage, and modern coding practices.
## Overview
The Verilog/SystemVerilog Language skill enables comprehensive HDL development for FPGA and ASIC designs, supporting:
- IEEE 1800-2017 SystemVerilog standard
- Verilog-2005 backward compatibility
- Proper always_ff, always_comb, always_latch usage
- SystemVerilog interfaces and modports
- Parameterized modules with localparam
- Packed and unpacked arrays
- Packages and imports