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uvm-methodology

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Deep expertise in Universal Verification Methodology (IEEE 1800.2) for FPGA verification

library/specializations/fpga-programming/skills/uvm-methodology/SKILL.md

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# UVM Methodology Skill

## Overview

Expert skill for Universal Verification Methodology (UVM) development following IEEE 1800.2 standards for comprehensive FPGA verification.

## Capabilities

- Generate UVM agent architecture (driver, monitor, sequencer)
- Create UVM environments and scoreboards
- Implement uvm_sequence and virtual sequences
- Configure UVM factory and config_db
- Implement functional coverage with covergroups
- Design UVM register models (RAL)
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