Not in the top 1,000 by GitHub stars

SPREsxm/claude-pcb-designer

Open Agent Skill for PCB design, review, deterministic calculations, DFM, and fabrication release. Works with Codex, Claude Code, KiCad, and EasyEDA/嘉立创EDA.

History

Review weekly changes to SKILL.md before updating. Dates mark the weeks in which we observed each version; checks apply to the recorded commits.

View weekly changes

SKILL.md

Week of Nov 2, 2026 · +0 / −0 lines

Before Local scripts → After Local scripts

d808009800f7 → d808009800f7

Compare on GitHub

Week of Oct 26, 2026 · Line counts unavailable

Before Not checked yet → After Local scripts

First observation → d808009800f7

No earlier version was observed for comparison.

Compare on GitHub

View on GitHubAdd to my skills

Verified commit d808009800f78fa37bc13c009cf6070301d34c23

git clone --filter=blob:none --no-checkout https://github.com/SPREsxm/claude-pcb-designer.git .hotskills/spresxm-claude-pcb-designer && git -C .hotskills/spresxm-claude-pcb-designer checkout --detach d808009800f78fa37bc13c009cf6070301d34c23 # Copy each selected skill directory from .hotskills/spresxm-claude-pcb-designer into .agents/skills/<skill-name>/
15GitHub stars
4stars in 7 days
1skill in this repository
0commits in 30 days

Heat

3.1
  • Star growth, last 7 daysNot available
  • Star growth, last 24 hoursNot available
  • Rank movement, last 7 daysNot available
  • Commits, last 30 daysNot available
  • Accounts asking about it through MCP, last 7 daysNot available
  • Hot votes this weekNot available

Heat never changes the order by stars, and sponsorship never touches it. How heat works

Stars over time

Oct 28, 2026Nov 4, 202615

30-day change not yet available: not enough history.

Individual skills in this repository

How it works

pcb-designer

When your agent uses it

Design, review, calculate, and release printed circuit boards for embedded, IoT, mixed-signal, power, and RF projects. Use when the user mentions PCB, schematic capture, layout, stackup, BOM, Gerber, pick-and-place, DRC/ERC, DFM/DFA, impedance, EMI/EMC, thermal design, EasyEDA/嘉立创EDA, KiCad, JLCPCB, or board bring-up. Not for mechanical-only enclosure design or IC-level silicon design.

What it loads into context

Frontmatter

200 tokens

Always available to the agent

SKILL.md

2,217 tokens

When the skill is activated

Reference documents

48,631 tokens

Loaded on request

Token counts are estimates. Scripts run separately; they are not counted as reference context.

The playbook

  1. Operating Rules
  2. Mode Router
  3. Design Workflow
  4. Severity Model
  5. Rule Precedence
  6. Output Contracts
  7. Bundled Tools
  8. Pairing With EasyEDA API
  9. Maintenance

Scripts executed separately

  • scripts/__init__.py
  • scripts/audit_release.py
  • scripts/generate_social_preview.py
  • scripts/install.py
  • scripts/package_skill.py
  • scripts/pcbcalc.py
  • scripts/validate_skill.py
  • tests/__init__.py
  • tests/test_audit_release.py
  • tests/test_package_skill.py
  • tests/test_pcbcalc.py
  • tests/test_validate_skill.py

Files

  • .github/CODEOWNERSasset11 bytes
  • .github/ISSUE_TEMPLATE/bug_report.ymlasset1,060 bytes
  • .github/ISSUE_TEMPLATE/config.ymlasset351 bytes
  • .github/ISSUE_TEMPLATE/design_review_request.ymlasset1,044 bytes
  • .github/ISSUE_TEMPLATE/feature_request.ymlasset940 bytes
  • .github/dependabot.ymlasset151 bytes
  • .github/pull_request_template.mddoc492 bytes
  • .github/release-notes/v3.0.0.mddoc1,739 bytes
  • .github/release-notes/v3.0.1.mddoc846 bytes
  • .github/workflows/release.ymlasset952 bytes
  • .github/workflows/validate.ymlasset1,158 bytes
  • .gitignoreasset540 bytes
  • AGENTS.mddoc1,001 bytes
  • CHANGELOG.mddoc1,992 bytes
  • CITATION.cffasset544 bytes
  • CODE_OF_CONDUCT.mddoc1,257 bytes
  • CONTRIBUTING.mddoc2,551 bytes
  • LICENSEasset1,071 bytes
  • README.mddoc9,568 bytes
  • README.zh-CN.mddoc5,720 bytes
  • SECURITY.mddoc1,097 bytes
  • SKILL.mdcore9,855 bytes
  • SKILL.mdcore9,855 bytes
  • SKILL.mdcore9,855 bytes
  • SKILL.mdcore9,855 bytes
  • agents/openai.yamlasset287 bytes
  • assets/social-preview.pngasset47,225 bytes
  • evals/evals.jsonasset10,287 bytes
  • examples/beginner-first-board.mddoc1,768 bytes
  • examples/esp32s3-flight-computer.mddoc5,089 bytes
  • examples/review-example.mddoc2,226 bytes
  • llms.txtdoc1,134 bytes
  • references/analog-design.mddoc5,712 bytes
  • references/bringup-and-validation.mddoc2,961 bytes
  • references/calculation-models.mddoc4,674 bytes
  • references/communication-interfaces.mddoc6,076 bytes
  • references/compliance-certification.mddoc5,644 bytes
  • references/component-selection.mddoc4,578 bytes
  • references/cost-optimization.mddoc5,600 bytes
  • references/design-intake.mddoc3,774 bytes
  • references/design-review-rubric.mddoc4,880 bytes
  • references/dfm-checklist.mddoc10,000 bytes
  • references/emc-guidelines.mddoc5,974 bytes
  • references/high-reliability.mddoc4,375 bytes
  • references/high-speed-digital.mddoc5,556 bytes
  • references/kicad-workflow.mddoc2,039 bytes
  • references/layer-choice.mddoc2,881 bytes
  • references/lceda-workflow.mddoc4,229 bytes
  • references/manufacturing-production.mddoc6,936 bytes
  • references/mcu-platforms.mddoc5,930 bytes
  • references/pcb-materials.mddoc6,534 bytes
  • references/power-design.mddoc4,717 bytes
  • references/protection-reliability.mddoc5,397 bytes
  • references/release-checklist.mddoc3,916 bytes
  • references/rf-design.mddoc5,659 bytes
  • references/schematic-review.mddoc3,432 bytes
  • references/stackup-and-impedance.mddoc5,571 bytes
  • references/standards-and-sources.mddoc2,795 bytes
  • references/testing-debug.mddoc4,210 bytes
  • references/thermal-design.mddoc4,007 bytes
  • rules/design-rules.jsonasset2,053 bytes
  • rules/fab-profiles.jsonasset3,660 bytes
  • scripts/__init__.pyruns53 bytes
  • scripts/audit_release.pyruns23,124 bytes
  • scripts/generate_social_preview.pyruns4,260 bytes
  • scripts/install.pyruns4,140 bytes
  • scripts/package_skill.pyruns2,689 bytes
  • scripts/pcbcalc.pyruns28,504 bytes
  • scripts/validate_skill.pyruns10,627 bytes
  • templates/bringup-log.mddoc1,366 bytes
  • templates/design-brief.mddoc1,908 bytes
  • templates/design-review-report.mddoc871 bytes
  • templates/fab-release-checklist.mddoc1,163 bytes
  • templates/power-budget.csvasset214 bytes
  • templates/supplier-rfq.mddoc1,710 bytes
  • tests/__init__.pyruns30 bytes
  • tests/test_audit_release.pyruns3,937 bytes
  • tests/test_package_skill.pyruns942 bytes
  • tests/test_pcbcalc.pyruns6,461 bytes
  • tests/test_validate_skill.pyruns413 bytes
Read SKILL.md

# PCB Designer

Use this skill as a senior hardware design partner. It covers requirements,
component selection, schematic review, stackup, placement, routing, power,
signal integrity, thermal design, manufacturing release, compliance, and
bring-up.

## Operating Rules

1. **Verify before asserting.** Datasheets, reference designs, current fab
   capabilities, and the user's actual files override generic guidance.
   Never invent pinouts, part numbers, LCSC IDs, ratings, prices, or stackup
   dimensions.
2. **Separate facts, assumptions, and recommendations.** State missing
View the complete source on GitHub

Skills included

  • pcb-designer

Repository facts

License
MIT
Created
Jun 19, 2026
Last pushed
Sep 13, 2026
Forks
0
Open issues
0
Project activity
Active

Before you install

Local scripts

Automated signals, not a guarantee

Checked Nov 7, 2026

Not fully analyzed: some files were too long, unreadable or missing. This never lowers the level.

Show 3 notes
  • SKILL.md:1 Analysis incomplete: Referenced executable target unavailable; not analyzed
  • SKILL.md:1 Analysis incomplete: Referenced executable target unavailable; not analyzed
  • SKILL.md:1 Analysis incomplete: Referenced executable target unavailable; not analyzed
Show all 61 signals by file

.github/ISSUE_TEMPLATE/config.yml

  • Network accessline 2
    contact_links:   - name: Security report     url: https://github.com/SPREsxm/claude-pcb-designer/security/advisories/new
  • Network accessline 3
    - name: Security report     url: https://github.com/SPREsxm/claude-pcb-designer/security/advisories/new     about: Report a security vulnerability privately.
  • Network accessline 4
    url: https://github.com/SPREsxm/claude-pcb-designer/security/advisories/new
  • Network accessline 5
    about: Report a security vulnerability privately.   - name: Design help     url: https://github.com/SPREsxm/claude-pcb-designer/discussions
  • Network accessline 6
    - name: Design help     url: https://github.com/SPREsxm/claude-pcb-designer/discussions     about: Ask a design question or share a board review.
  • Network accessline 7
    url: https://github.com/SPREsxm/claude-pcb-designer/discussions

.github/release-notes/v3.0.0.md

  • Network accessline 25
    git clone https://github.com/SPREsxm/claude-pcb-designer.git
  • Network accessline 47
    Full changes are in [CHANGELOG.md](https://github.com/SPREsxm/claude-pcb-designer/blob/master/CHANGELOG.md).

.gitignore

  • Access to secretsline 61
    [Credential-related source omitted]

CHANGELOG.md

  • Network accessline 3
    All notable changes follow [Keep a Changelog](https://keepachangelog.com/) and

CITATION.cff

  • Network accessline 6
    - family-names: "SPREsxm"     alias: "RocketBlackBox" repository-code: "https://github.com/SPREsxm/claude-pcb-designer"
  • Network accessline 7
    alias: "RocketBlackBox" repository-code: "https://github.com/SPREsxm/claude-pcb-designer" url: "https://github.com/SPREsxm/claude-pcb-designer"
  • Network accessline 8
    repository-code: "https://github.com/SPREsxm/claude-pcb-designer"
  • Network accessline 9
    url: "https://github.com/SPREsxm/claude-pcb-designer"

README.md

  • Network accessline 10
    [![CI](https://github.com/SPREsxm/claude-pcb-designer/actions/workflows/validate.yml/badge.svg)](https://github.com/SPREsxm/claude-pcb-designer/actions/workflows/validate.yml)
  • Network accessline 11
    [![Release](https://img.shields.io/github/v/tag/SPREsxm/claude-pcb-designer?label=release)](https://github.com/SPREsxm/claude-pcb-designer/releases)
  • Network accessline 12
    [![License](https://img.shields.io/github/license/SPREsxm/claude-pcb-designer)](LICENSE)
  • Network accessline 13
    [![Stars](https://img.shields.io/github/stars/SPREsxm/claude-pcb-designer?style=social)](https://github.com/SPREsxm/claude-pcb-designer/stargazers)
  • Network accessline 24
    It works with Codex, Claude Code, and other tools that understand the [Agent Skills](https://agentskills.io/) format.
  • Network accessline 25
    [Agent Skills](https://agentskills.io/) format.
  • Network accessline 62
    git clone https://github.com/SPREsxm/claude-pcb-designer.git
  • Network accessline 272
    [![Star History Chart](https://api.star-history.com/svg?repos=SPREsxm/claude-pcb-designer&type=Date)](https://star-history.com/#SPREsxm/claude-pcb-designer&Date)

README.zh-CN.md

  • Network accessline 9
    [![CI](https://github.com/SPREsxm/claude-pcb-designer/actions/workflows/validate.yml/badge.svg)](https://github.com/SPREsxm/claude-pcb-designer/actions/workflows/validate.yml)
  • Network accessline 10
    [![Release](https://img.shields.io/github/v/tag/SPREsxm/claude-pcb-designer?label=release)](https://github.com/SPREsxm/claude-pcb-designer/releases)
  • Network accessline 11
    [![License](https://img.shields.io/github/license/SPREsxm/claude-pcb-designer)](LICENSE)
  • Network accessline 12
    [![Stars](https://img.shields.io/github/stars/SPREsxm/claude-pcb-designer?style=social)](https://github.com/SPREsxm/claude-pcb-designer/stargazers)
  • Network accessline 22
    支持 Codex、Claude Code,以及兼容 [Agent Skills](https://agentskills.io/) 的其他工具。
  • Network accessline 23
    [Agent Skills](https://agentskills.io/) 的其他工具。
  • Network accessline 51
    git clone https://github.com/SPREsxm/claude-pcb-designer.git

SECURITY.md

  • Network accessline 8
    https://github.com/SPREsxm/claude-pcb-designer/security/advisories/new

SKILL.md

  • Network accessline 6
    author: SPREsxm   version: "3.0.1"   repository: https://github.com/SPREsxm/claude-pcb-designer
  • Network accessline 7
    version: "3.0.1"   repository: https://github.com/SPREsxm/claude-pcb-designer   keywords:
  • Network accessline 8
    repository: https://github.com/SPREsxm/claude-pcb-designer

llms.txt

  • Network accessline 6
    Repository: https://github.com/SPREsxm/claude-pcb-designer
  • Network accessline 12
    - [Skill entrypoint](https://github.com/SPREsxm/claude-pcb-designer/blob/master/SKILL.md)
  • Network accessline 13
    - [English README](https://github.com/SPREsxm/claude-pcb-designer/blob/master/README.md)
  • Network accessline 14
    - [Chinese README](https://github.com/SPREsxm/claude-pcb-designer/blob/master/README.zh-CN.md)
  • Network accessline 15
    - [Contributing](https://github.com/SPREsxm/claude-pcb-designer/blob/master/CONTRIBUTING.md)
  • Network accessline 16
    - [Changelog](https://github.com/SPREsxm/claude-pcb-designer/blob/master/CHANGELOG.md)

references/standards-and-sources.md

  • Network accessline 56
    {   "name": "example-fab",   "source_url": "https://example.invalid/capabilities",
  • Network accessline 57
    "name": "example-fab",   "source_url": "https://example.invalid/capabilities",   "verified_on": "2026-09-13",
  • Network accessline 58
    "source_url": "https://example.invalid/capabilities",

rules/fab-profiles.json

  • Network accessline 56
    "id": "jlcpcb-common",       "name": "JLCPCB common prototype starting point",       "source_url": "https://jlcpcb.com/capabilities/pcb-capabilities",
  • Network accessline 57
    "name": "JLCPCB common prototype starting point",       "source_url": "https://jlcpcb.com/capabilities/pcb-capabilities",       "verified_on": null,
  • Network accessline 58
    "source_url": "https://jlcpcb.com/capabilities/pcb-capabilities",
  • Network accessline 82
    "id": "generic-osh-park",       "name": "OSH Park-style two-layer prototype",       "source_url": "https://docs.oshpark.com/services/two-layer/",
  • Network accessline 83
    "name": "OSH Park-style two-layer prototype",       "source_url": "https://docs.oshpark.com/services/two-layer/",       "verified_on": null,
  • Network accessline 84
    "source_url": "https://docs.oshpark.com/services/two-layer/",

scripts/__init__.py

  • Executable scriptline 1
    Executable file

scripts/audit_release.py

  • Executable scriptline 1
    #!/usr/bin/env python3

scripts/generate_social_preview.py

  • Executable scriptline 1
    #!/usr/bin/env python3

scripts/install.py

  • Executable scriptline 1
    #!/usr/bin/env python3
  • Access to secretsline 27
    [Credential-related source omitted]

scripts/package_skill.py

  • Executable scriptline 1
    #!/usr/bin/env python3

scripts/pcbcalc.py

  • Executable scriptline 1
    #!/usr/bin/env python3

scripts/validate_skill.py

  • Executable scriptline 1
    #!/usr/bin/env python3

tests/__init__.py

  • Executable scriptline 1
    Executable file

tests/test_audit_release.py

  • Executable scriptline 1
    Executable file

tests/test_package_skill.py

  • Executable scriptline 1
    Executable file

tests/test_pcbcalc.py

  • Executable scriptline 1
    Executable file

tests/test_validate_skill.py

  • Executable scriptline 1
    Executable file

How the signals fit together

Facts from a static read of the files at the pinned commit. They describe what the code does, not why.

Some files could not be read; the facts below still hold.

Signal confidence: 44 facts

Works with

Agent compatibility, from the files in this repository
AgentStatusEvidenceInstall to
Claude CodeCompatibleStandard SKILL.md SKILL.md.claude/skills/<skill-name>/
CodexNativeManifest AGENTS.md.agents/skills/<skill-name>/
CursorCompatibleStandard SKILL.md SKILL.md.cursor/skills/<skill-name>/
Gemini CLICompatibleStandard SKILL.md SKILL.md.gemini/skills/<skill-name>/
GitHub CopilotCompatibleStandard SKILL.md SKILL.md.github/skills/<skill-name>/
OpenCodeCompatibleStandard SKILL.md SKILL.md.opencode/skills/<skill-name>/
  • Native The repository ships a manifest, folder or frontmatter field for this agent.
  • Compatible A standard SKILL.md that this agent can read.
  • Unknown No evidence either way.

Derived automatically from paths, manifests and frontmatter. Not tested on each agent.