Individual skill
assembly-riscv
Use when reading or writing RV32/RV64 assembly, inline asm in C, the RISC-V psABI, IMAFD extension naming, compressed instructions, or QEMU RISC-V debugging.
.devin/skills/assembly-riscv/SKILL.md
Source commit b0e8ce89a19fac880251dc3ea1babfeb4503a4fe
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- Matches the observed repository HEAD
- Yes
- Scanner rules are current
- Yes
- Repository scan complete
- No
- Skill scan complete
- No
- Observed behavior
- Instructions only
- Last checked
- Nov 4, 2026
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Repository context
- Repository stars (not skill ratings)
- 55
- Repository last updated
- Sep 28, 2026
- License
- Apache-2.0
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SKILL.mdcore · 6,134 bytesSKILL.mdcore · 6,134 bytesSKILL.mdcore · 6,134 bytesagents/openai.yamlasset · 225 bytesreferences/riscv-abi.mddoc · 3,176 bytes
Read excerpt
# RISC-V assembly
RISC-V is a small load-store ISA grown through named extensions. This skill covers user-mode RV32 and RV64 assembly, the psABI register contract, and the QEMU loop.
## Contract
| Field | Bound contract |
|---|---|
| Trigger | The task writes inline asm or assembly for RV32 or RV64, decodes ABI register names, names an ISA extension string, enables compressed instructions, or debugs RISC-V under QEMU with GDB. |
| Authority | Read-only. The skill explains and drafts; edits land through the normal coding path. No remote mutation. |
| Side effect | None. |
| Done | The drafted assembly assembles for the named base ISA and extensions, or the compiler output under discussion is explained register by register. |
## Inputs