Individual skill
interrupts-and-exceptions-baremetal
Use when writing Cortex-M NVIC ISRs, configuring priorities, handling HardFault, tail-chaining, or measuring interrupt latency. Not for the vector table itself: use baremetal-startup.
.devin/skills/interrupts-and-exceptions-baremetal/SKILL.md
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SKILL.mdcore · 7,347 bytesagents/openai.yamlasset · 216 bytes
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# Interrupts and exceptions on bare metal
## Contract
| Field | Bound contract |
|---|---|
| Trigger | A peripheral interrupt must be enabled and prioritized, an ISR must share data with the main loop, a HardFault appears after interrupts are enabled, or interrupt latency must be measured or reduced on Cortex-M. |
| Authority | Read-only: emits NVIC configuration, ISR templates, fault-decoding code, and measurement steps to chat; the user places them in the firmware. Rollback is not needed because no file is written. No remote mutation. |
| Side effect | Chat output only. |
| Done | The IRQ is enabled with an explicit priority, the ISR clears its flag the way the reference manual states, shared data crosses the boundary through a critical section or a lock-free buffer, and fault decoding names the stacked PC and the fault status registers for the core. |
## Inputs
- Target core (Cortex-M0+, M3, M4, M7, M33) and the vendor CMSIS device header.