Individual skill
emc
EMC pre-compliance risk analysis for KiCad PCB designs — 18 check categories, 44 rule IDs covering ground planes, decoupling, I/O filtering, switching harmonics, clock routing, differential pair skew, board edge radiation, PDN impedance, return paths, crosstalk, ESD protection, shielding, and magnetic leakage from switching inductors. Produces severity-ranked risk report with pre-compliance test plan. Supports FCC Part 15, CISPR 32, CISPR 25 (automotive), MIL-STD-461G. SPICE-enhanced when available. Use when the user asks about EMC, EMI, radiated/conducted emissions, FCC compliance, CE marking, CISPR, ground plane issues, decoupling strategy, clock routing EMC, switching noise, differential pair skew, or whether their board will pass EMC testing. Also for "will this pass FCC?", "check my EMC", "is my ground plane okay?", "check my decoupling", or "generate an EMC test plan".
plugins/aklofas/kicad-happy/skills/emc/SKILL.md
Source commit d780783eba4ecc7c8b9429f95c9362df95f07c61
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- Yes
- Scanner rules are current
- Yes
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- Observed behavior
- Network or broad shell
- Last checked
- Nov 4, 2026
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- 1,532
- Repository last updated
- Nov 6, 2026
- License
- Apache-2.0
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SKILL.mdcore · 11,184 bytesSKILL.mdcore · 11,184 bytesSKILL.mdcore · 11,184 bytesSKILL.mdcore · 11,184 bytesSKILL.mdcore · 11,184 bytesreferences/emc-methodology.mddoc · 10,238 bytesreferences/emc-standards.mddoc · 5,806 bytesreferences/pcb-emc-rules.mddoc · 25,273 bytesscripts/analyze_emc.pyruns · 27,988 bytesscripts/emc_envelope.pyruns · 13,414 bytesscripts/emc_formulas.pyruns · 50,884 bytesscripts/emc_rules.pyruns · 186,543 bytesscripts/emc_spice.pyruns · 24,929 bytes
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# EMC Pre-Compliance Skill
Automated EMC risk analysis for KiCad PCB designs. Identifies the most common causes of EMC test failures using geometric rule checks, analytical emission formulas, and optional SPICE simulation.
**This is a risk analyzer, not a compliance predictor.** It catches ~70% of common EMC design mistakes before fabrication. It cannot guarantee FCC/CISPR compliance — only a calibrated measurement in an accredited lab can do that. But it can reduce the first-spin failure rate from ~50% toward ~20-30%, potentially saving $5K-$50K per avoided board respin.
## Related Skills
| Skill | Purpose |
|-------|---------|
| `kicad` | Schematic/PCB analysis — produces the analyzer JSON this skill consumes |
| `kicad` (thermal) | Thermal hotspot analysis — MLCC derating and ferrite/inductor overheating findings can amplify EMC decoupling and filter issues (an over-stressed MLCC degrades; a hot ferrite drifts impedance). Worth cross-checking when EMC flags DC-001/DC-002 or EF-001/EF-002. |
| `spice` | SPICE simulation — provides simulator backend for SPICE-enhanced PDN/filter checks |
